[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Jessica Paquette via Phabricator via llvm-commits]

paquette added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/machineoutliner.mir:1-2
+# RUN: llc -march riscv32 -x mir < %s | FileCheck -check-prefix=RV32I %s
+# RUN: llc -march riscv32 -x mir -enable-machine-outliner < %s \
+# RUN: | FileCheck -check-prefix=RV32I-MO %s
----------------
You probably want -verify-machineinstrs on each of these.


================
Comment at: llvm/test/CodeGen/RISCV/machineoutliner.mir:7-11
+  entry:
+    %0 = add i32 %a, 17
+    %1 = or i32 %b, 1023
+    %2 = and i32 %0, %1
+    ret i32 %2
----------------
I don't think you actually need the body of the IR functions here. You can make each function void, and just return:

e.g.

```
define i32 @outline_0(i32 %a, i32 %b) #0 { ret void }
```

If it weren't for the section checks, you wouldn't need the IR at all. It only needs to be there when you look back at the IR in some way in the pass. 


================
Comment at: llvm/test/CodeGen/RISCV/machineoutliner.mir:59
+
+  declare void @llvm.stackprotector(i8*, i8**) #0
+
----------------
I'm pretty sure you can remove this.


================
Comment at: llvm/test/CodeGen/RISCV/machineoutliner.mir:61
+
+  attributes #0 = { nounwind }
+
----------------
This isn't checked/used by the outliner, so you can remove it from the IR.


================
Comment at: llvm/test/CodeGen/RISCV/machineoutliner.mir:76
+body:             |
+  bb.0.entry:
+    ; RV32I-LABEL: outline_0:
----------------
If you do remove the bulk of the IR code, you'll need to rename the BB labels to `bb.0`.


================
Comment at: llvm/test/CodeGen/RISCV/machineoutliner.mir:81
+    ; RV32I-MO-LABEL: outline_0:
+    ; RV32I-MO:         call t0, OUTLINED_FUNCTION_0
+    liveins: $x10, $x11
----------------
It would be good to check the contents of the outlined functions as well.

E.g. OUTLINED_FUNCTION_0 should contain the ORI/ADDI/AND sequence.

(It's possible that utils/update_mir_test_checks.py can generate all of the checks you want here, but I'm not sure if it can handle functions being created.)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210