[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V
Lewis Revill via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 2 05:54:20 PDT 2019
lewis-revill updated this revision to Diff 218344.
lewis-revill added a comment.
Updated the test to an MIR-based test, and added checks for the cases where outlining cannot be done.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D66210/new/
https://reviews.llvm.org/D66210
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/machineoutliner.mir
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