[PATCH] D67136: GlobalISel/TableGen: Handle REG_SEQUENCE patterns

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: dsanders, paquette, aditya_nandakumar, aemerson.
Herald added subscribers: Petar.Avramovic, rovka, nhaehnle, wdng, jvesely.

The scalar f64 patterns don't work yet because they fail on multiple
results from the unused implicit def of scc in the result bit
operation.


https://reviews.llvm.org/D67136

Files:
  lib/Target/AMDGPU/SIInstructions.td
  test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
  test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
  test/TableGen/GlobalISelEmitterRegSequence.td
  utils/TableGen/GlobalISelEmitter.cpp

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