[PATCH] D67021: [DAGCombiner] improve throughput of shift+logic+shift
Roman Lebedev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 31 15:16:43 PDT 2019
lebedev.ri added a comment.
I think this looks ok, some comments.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7251-7252
+ const APInt *C0;
+ if (matchFirstShift(LogicOp.getOperand(0), C0)) {
+ X = LogicOp.getOperand(0).getOperand(0);
+ Y = LogicOp.getOperand(1);
----------------
I think you want to make `matchFirstShift()` return that `X`.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7266
+ SDValue NewShift1 = DAG.getNode(ShiftOpcode, DL, VT, X, ShiftSum);
+ SDValue NewShift2 = DAG.getNode(ShiftOpcode, DL, VT, Y, Shift->getOperand(1));
+ return DAG.getNode(LogicOpcode, DL, VT, NewShift1, NewShift2);
----------------
It would be less confusing to `C1 = Shift->getOperand(1);` somewhere up there, and use `C1` here.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D67021/new/
https://reviews.llvm.org/D67021
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