[PATCH] D62341: [DAGCombine][X86][AArch64][AMDGPU][MIPS][PPC] (sub x, c) -> (add x, -c) vector edition.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri updated this revision to Diff 217380.
lebedev.ri marked 3 inline comments as done.
lebedev.ri edited the summary of this revision.
lebedev.ri added a comment.
Herald added subscribers: steven.zhang, wuzish, MaskRay, hiraditya.

Rebased.
AMDGPU regressions are no more (@arsenm, thanks!)
Everything else is still the same - some PPC and MIPS regressions remain.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62341/new/

https://reviews.llvm.org/D62341

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
  llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
  llvm/test/CodeGen/AArch64/vec_cttz.ll
  llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
  llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
  llvm/test/CodeGen/Mips/msa/arithmetic.ll
  llvm/test/CodeGen/Mips/msa/i5-s.ll
  llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
  llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
  llvm/test/CodeGen/PowerPC/vec_clz.ll
  llvm/test/CodeGen/PowerPC/vec_splat.ll
  llvm/test/CodeGen/X86/addsub-constant-folding.ll
  llvm/test/CodeGen/X86/avx-shift.ll
  llvm/test/CodeGen/X86/avx2-shift.ll
  llvm/test/CodeGen/X86/combine-sdiv.ll
  llvm/test/CodeGen/X86/combine-sub.ll
  llvm/test/CodeGen/X86/known-signbits-vector.ll
  llvm/test/CodeGen/X86/packss.ll
  llvm/test/CodeGen/X86/prefer-avx256-lzcnt.ll
  llvm/test/CodeGen/X86/sadd_sat_vec.ll
  llvm/test/CodeGen/X86/sink-addsub-of-const.ll
  llvm/test/CodeGen/X86/ssub_sat_vec.ll
  llvm/test/CodeGen/X86/vector-fshl-128.ll
  llvm/test/CodeGen/X86/vector-fshl-256.ll
  llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
  llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
  llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
  llvm/test/CodeGen/X86/vector-lzcnt-128.ll
  llvm/test/CodeGen/X86/vector-lzcnt-256.ll
  llvm/test/CodeGen/X86/vector-lzcnt-512.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
  llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
  llvm/test/CodeGen/X86/vector-trunc-math.ll
  llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll
  llvm/test/CodeGen/X86/widen_arith-4.ll
  llvm/test/CodeGen/X86/widen_arith-5.ll
  llvm/test/CodeGen/X86/widen_cast-4.ll
  llvm/test/CodeGen/X86/x86-shifts.ll

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