[PATCH] D66801: [X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb marked 2 inline comments as done.
andreadb added inline comments.


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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:821
+//  AVX Conditional SIMD Packed Stores - VMASKMOVP
+//  SSE2/AVX Sttore Selected Bytes of Double Quadword - (V)MASKMOVDQ
+///////////////////////////////////////////////////////////////////////////////
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RKSimon wrote:
> Store
Thanks. I will fix it.


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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:858
+]>;
+def : SchedAlias<WriteFMaskedStoreY, JWriteFMaskedStoreY>;
+
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RKSimon wrote:
> Would we be better off just splitting WriteFMaskedStore into WriteFMaskedStore32 + WriteFMaskedStore64?
I have been thinking about it before sending this patch. The possibility of adding new classes for conditional writes was not so bad to start.
However, btver2 is currently the only model that requires to special case the PS/PD variants. So, eventually I opted for this solution because it seemed like a good compromise. Maybe we could revisit this decision later on if we see that other models also require to special case these writes. What do you think?



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