[PATCH] D66801: [X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:821
+//  AVX Conditional SIMD Packed Stores - VMASKMOVP
+//  SSE2/AVX Sttore Selected Bytes of Double Quadword - (V)MASKMOVDQ
+///////////////////////////////////////////////////////////////////////////////
----------------
Store


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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:858
+]>;
+def : SchedAlias<WriteFMaskedStoreY, JWriteFMaskedStoreY>;
+
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Would we be better off just splitting WriteFMaskedStore into WriteFMaskedStore32 + WriteFMaskedStore64?


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  https://reviews.llvm.org/D66801/new/

https://reviews.llvm.org/D66801