[PATCH] D66882: [DAGCombiner] Match (add X, X) as (shl X, 1) when detecting rotate.
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 28 07:28:55 PDT 2019
RKSimon added a reviewer: spatel.
RKSimon added inline comments.
================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6019
+ Shift = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0),
+ DAG.getShiftAmountConstant(1, VT, DL));
+ return true;
----------------
Is there any easy way that we can avoid creating nodes like this? Its purpose seems purely to be matched again later.
Repository:
rL LLVM
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https://reviews.llvm.org/D66882/new/
https://reviews.llvm.org/D66882
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