[PATCH] D66519: [ARM] Fix lsrl with a 128/256 bit shift amount or a shift of 32

[Sam Tebbs via Phabricator via llvm-commits]

samtebbs updated this revision to Diff 216396.
samtebbs marked an inline comment as done.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66519/new/

https://reviews.llvm.org/D66519

Files:
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/shift_parts.ll
  llvm/test/CodeGen/Thumb2/mve-abs.ll
  llvm/test/CodeGen/Thumb2/mve-div-expand.ll
  llvm/test/CodeGen/Thumb2/mve-vcvt.ll

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