[PATCH] D66519: [ARM] Fix lsrl with a 128/256 bit shift amount or a shift of 32
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 21 06:12:50 PDT 2019
dmgreen added inline comments.
================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:5940
+ // If the shift amount is greater than 32 or has a greater bitwidth than 64 then do the default optimisation
+ if (ShAmt->getValueType(0).getSizeInBits() > 64 || (Con && Con->getZExtValue() >= 32))
return SDValue();
----------------
You can format these long lines
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D66519/new/
https://reviews.llvm.org/D66519
More information about the llvm-commits
mailing list