[PATCH] D66515: [MVT] Add v16f16 and v32f16 vectors.
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 21 02:05:03 PDT 2019
RKSimon added inline comments.
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Comment at: llvm/include/llvm/CodeGen/ValueTypes.td:165
+def FlagVT : ValueType<0 , 130>; // Pre-RA sched glue
+def isVoid : ValueType<0 , 131>; // Produces no value
+def untyped: ValueType<8 , 132>; // Produces an untyped value
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Would it not make sense to have a comment here about keeping isVoid in sync with llvm/test/TableGen/intrinsic-varargs.td ?
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Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp:161
+ setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::v32f32, MVT::v32f16, Expand);
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Do these have test coverage already?
Do these need to be part of this patch or should they be in a followup?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D66515/new/
https://reviews.llvm.org/D66515
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