[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:496
+  for (; I != E; ++I)
+    SequenceSize += getInstSizeInBytes(*I);
+
----------------
luismarques wrote:
> This might be pessimistic when the instructions are compressible. Suddenly the outlined amount vs the overhead math might not quite be realistic. I think it's worth devising a test to try to explore how much of a problem that is, and if we can compensate for it by, say, tweaking the overhead numbers, or determining if the instruction is likely to be compressible, or being conservative regarding the instruction size when targeting RVC.
Wouldn't you want getInstSizeInBytes to account for compression for other reasons, anyway?  For example, to avoid triggering branch relaxation when it isn't necessary.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:503
+
+  // RISCV::PseudoRET = 8 bytes.
+  unsigned FrameOverhead = 8;
----------------
> RISCV::PseudoRET = 8 bytes.

I don't understand the math here.


Repository:
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  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210