[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Luís Marques via Phabricator via llvm-commits]

luismarques requested changes to this revision.
luismarques added inline comments.
This revision now requires changes to proceed.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:471
+bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(
+    MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
+  return true;
----------------
AArch64 has more checks, some of which seem like could be relevant for us. Checking for section markings, link once, etc.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:481
+  RS.enterBasicBlock(MBB);
+  return !RS.isRegUsed(RISCV::X5);
+}
----------------
If we are only going to support one possible register for now, shouldn't it be the one least likely to already be in use? Wouldn't that be t6 (x31)?


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:496
+  for (; I != E; ++I)
+    SequenceSize += getInstSizeInBytes(*I);
+
----------------
This might be pessimistic when the instructions are compressible. Suddenly the outlined amount vs the overhead math might not quite be realistic. I think it's worth devising a test to try to explore how much of a problem that is, and if we can compensate for it by, say, tweaking the overhead numbers, or determining if the instruction is likely to be compressible, or being conservative regarding the instruction size when targeting RVC.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210