[PATCH] D63731: [AMDGPU] Prevent VGPR copies from moving across the EXEC mask definitions
Alexander via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 15 07:58:59 PDT 2019
alex-t updated this revision to Diff 215401.
alex-t added a comment.
Suggested nits added.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D63731/new/
https://reviews.llvm.org/D63731
Files:
llvm/include/llvm/CodeGen/MachineInstr.h
llvm/lib/CodeGen/PeepholeOptimizer.cpp
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
Index: llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
+++ llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
@@ -882,7 +882,7 @@
---
# GCN-LABEL: name: constant_fold_lshl_or_reg0_immreg_immreg{{$}}
-# GCN: %3:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec, implicit $exec
+# GCN: %3:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
# GCN-NEXT: S_ENDPGM 0, implicit %3
name: constant_fold_lshl_or_reg0_immreg_immreg
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4207,6 +4207,15 @@
// Try to eliminate the copy if it is copying an immediate value.
if (Def->isMoveImmediate())
FoldImmediate(*Copy, *Def, OpReg, &MRI);
+
+ bool ImpDef = Def->isImplicitDef();
+ while (!ImpDef && Def && Def->isCopy()) {
+ Def = MRI.getUniqueVRegDef(Def->getOperand(1).getReg());
+ ImpDef = Def && Def->isImplicitDef();
+ }
+ if (!RI.isSGPRClass(DstRC) && !Copy->readsRegister(AMDGPU::EXEC, &RI) &&
+ !ImpDef)
+ Copy->addOperand(MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
}
// Emit the actual waterfall loop, executing the wrapped instruction for each
Index: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -612,6 +612,13 @@
return;
UseMI->setDesc(TII->get(MovOp));
+ MachineInstr::mop_iterator ImpOpI = UseMI->implicit_operands().begin();
+ MachineInstr::mop_iterator ImpOpE = UseMI->implicit_operands().end();
+ while (ImpOpI != ImpOpE) {
+ MachineInstr::mop_iterator Tmp = ImpOpI;
+ ImpOpI++;
+ UseMI->RemoveOperand(UseMI->getOperandNo(Tmp));
+ }
CopiesToReplace.push_back(UseMI);
} else {
if (UseMI->isCopy() && OpToFold.isReg() &&
Index: llvm/lib/CodeGen/PeepholeOptimizer.cpp
===================================================================
--- llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -1808,7 +1808,11 @@
assert(Def->isCopy() && "Invalid definition");
// Copy instruction are supposed to be: Def = Src.
// If someone breaks this assumption, bad things will happen everywhere.
- assert(Def->getNumOperands() == 2 && "Invalid number of operands");
+ // There may be implicit uses preventing the copy to be moved across
+ // some target specific register definitions
+ assert(Def->getNumOperands() - Def->getNumImplicitOperands() == 2 &&
+ "Invalid number of operands");
+ assert(!Def->hasImplicitDef() && "Only implicit uses are allowed");
if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
// If we look for a different subreg, it means we want a subreg of src.
Index: llvm/include/llvm/CodeGen/MachineInstr.h
===================================================================
--- llvm/include/llvm/CodeGen/MachineInstr.h
+++ llvm/include/llvm/CodeGen/MachineInstr.h
@@ -427,6 +427,22 @@
return getNumExplicitDefs() + MCID->getNumImplicitDefs();
}
+ /// Returns true if the instruction has implicit definition.
+ bool hasImplicitDef() const {
+ for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
+ I != E; ++I) {
+ const MachineOperand &MO = getOperand(I);
+ if (MO.isDef() && MO.isImplicit())
+ return true;
+ }
+ return false;
+ }
+
+ /// Returns the implicit operands number.
+ unsigned getNumImplicitOperands() const {
+ return getNumOperands() - getNumExplicitOperands();
+ }
+
/// Return true if operand \p OpIdx is a subregister index.
bool isOperandSubregIdx(unsigned OpIdx) const {
assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&
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