[PATCH] D63731: [AMDGPU] Prevent VGPR copies from moving across the EXEC mask definitions

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet added a comment.

LGTM for the generic part.

Nits below.



================
Comment at: llvm/include/llvm/CodeGen/MachineInstr.h:430
 
+  /// Returns true if the instruction has implicit definition
+  bool hasImplicitDef() const {
----------------
Nit: Period at the end of sentence.


================
Comment at: llvm/include/llvm/CodeGen/MachineInstr.h:435
+      const MachineOperand &MO = getOperand(I);
+      if (MO.isReg() && MO.isImplicit() && MO.isDef())
+        return true;
----------------
MO.isDef implies MO.isReg.
You can simplify the check.


================
Comment at: llvm/include/llvm/CodeGen/MachineInstr.h:448
+      if (MO.isReg() && MO.isImplicit())
+        NumImpOp++;
+    }
----------------
Implicit operands must be registers.
Thus, you can simplify all this with:
```
return getNumOperands() - getNumExplicitOperands();
```



CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63731/new/

https://reviews.llvm.org/D63731