[PATCH] D66285: [ARM] Correct register for narrowing and widening MVE loads and stores.

[Oliver Stannard (Linaro) via Phabricator via llvm-commits]

ostannard added inline comments.


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Comment at: llvm/lib/Target/ARM/Thumb2InstrInfo.cpp:656
+    if ((unsigned)Offset <= Mask * Scale &&
+        (Register::isVirtualRegister(FrameReg) ||
+         RegClass->contains(FrameReg))) {
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Is it possible to get here with a virtual register of the wrong class? I think we'd need a call to `constrainRegClass` here in that case.


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  https://reviews.llvm.org/D66285/new/

https://reviews.llvm.org/D66285