[PATCH] D66285: [ARM] Correct register for narrowing and widening MVE loads and stores.

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: t.p.northover, simon_tatham, SjoerdMeijer, samparker, ostannard, efriedma.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

The widening and narrowing MVE instructions like VLDRH.32 are only permitted to use low "thumb1" registers. This means that if they are used for a stack slots, where the register used is only decided during frame setup, we need to be able to correctly pick a thumb1 register over a normal GPR.

This attempts to add the required logic into eliminateFrameIndex and rewriteT2FrameIndex, only picking the FrameReg if it is a valid register for the operands register class, and picking a valid scratch register for the register class.


https://reviews.llvm.org/D66285

Files:
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
  llvm/test/CodeGen/Thumb2/mve-stack.ll

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