[PATCH] D66236: [SDAG][x86] check for relaxed math when matching an FP reduction

[Sanjay Patel via Phabricator via llvm-commits]

spatel updated this revision to Diff 215234.
spatel marked an inline comment as done.
spatel added a comment.

Patch updated:

1. Switch flag requirements based on opcode (only FADD handled for now).
2. Added partial reduction tests (rL368913 <https://reviews.llvm.org/rL368913>).
3. Added negative test for mismatch on fast-math-flags.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66236/new/

https://reviews.llvm.org/D66236

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/haddsub.ll
  llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll

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