[PATCH] D66236: [SDAG][x86] check for relaxed math when matching an FP reduction

[Sanjay Patel via Phabricator via llvm-commits]

spatel marked 3 inline comments as done.
spatel added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:9013
+      return SDValue();
+  }
 
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RKSimon wrote:
> Is this satisfactory for all possible float ops (FMUL/FMIN/etc)? Also, shouldn't we be testing this at every stage?
Good point. We don't have any FP callers for this besides the FADD that's being added in this patch. FMUL would not need 'nsz', and I'm not sure about FMIN/FMAX:
    /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
    VECREDUCE_FMAX, VECREDUCE_FMIN,

I think the safe thing for this patch is to handle FADD and assert on the other opcodes until we have an actual caller and know exactly what that behavior should be.

For the flags, I'm following the FMF semantics that we use in IR: the final calculation alone determines what relaxations are allowed for any intermediate calcs leading up to that value. I've added a test to confirm that logic.


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  https://reviews.llvm.org/D66236/new/

https://reviews.llvm.org/D66236