[PATCH] D66169: [X86][CostModel] Adjust the costs of ZERO_EXTEND/SIGN_EXTEND with less than 128-bit inputs

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM - I agree the AVX1 256-bit result cases might need further tweaking (especially for extension ratio = 2 as we can cheaply use movx+unpckh), but that can wait for now.



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Comment at: llvm/test/Transforms/SLPVectorizer/X86/sext.ll:611
+; AVX1-NEXT:    [[X2:%.*]] = sext i16 [[I2]] to i64
+; AVX1-NEXT:    [[X3:%.*]] = sext i16 [[I3]] to i64
+; AVX1-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
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Please can you raise a bug about the lower v2i8 sext vectorizing but the upper 2 x i8 not?


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https://reviews.llvm.org/D66169