[PATCH] D66169: [X86][CostModel] Adjust the costs of ZERO_EXTEND/SIGN_EXTEND with less than 128-bit inputs

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

Now that we legalize by widening, the element types here won't change. Previously these were modeled as the elements being widened and then the instruction might become an AND or SHL/ASHR pair. But now they'll become something like a ZERO_EXTEND_VECTOR_INREG/SIGN_EXTEND_VECTOR_INREG.

For AVX2, when the destination type is legal its clear the cost should be 1 since we have extend instructions that can produce 256 bit vectors from less than 128 bit vectors. I'm a little less sure about AVX1 costs, but I think the ones I changed were definitely too high, but they might still be too high.


https://reviews.llvm.org/D66169

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/cast.ll
  llvm/test/Analysis/CostModel/X86/extend.ll
  llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll
  llvm/test/Transforms/SLPVectorizer/X86/cast.ll
  llvm/test/Transforms/SLPVectorizer/X86/sext.ll
  llvm/test/Transforms/SLPVectorizer/X86/zext.ll

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