[llvm] r368775 - [AArch64][GlobalISel] RBS: Treat s128s like vectors when unmerging.

[Amara Emerson via llvm-commits]

Author: aemerson
Date: Tue Aug 13 16:51:20 2019
New Revision: 368775

URL: http://llvm.org/viewvc/llvm-project?rev=368775&view=rev
Log:
[AArch64][GlobalISel] RBS: Treat s128s like vectors when unmerging.

The destinations should be FPRs (for now).

Differential Revision: https://reviews.llvm.org/D66184

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=368775&r1=368774&r2=368775&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Tue Aug 13 16:51:20 2019
@@ -768,7 +768,7 @@ AArch64RegisterBankInfo::getInstrMapping
     LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
     // UNMERGE into scalars from a vector should always use FPR.
     // Likewise if any of the uses are FP instructions.
-    if (SrcTy.isVector() ||
+    if (SrcTy.isVector() || SrcTy == LLT::scalar(128) ||
         any_of(MRI.use_instructions(MI.getOperand(0).getReg()),
                [&](MachineInstr &MI) { return onlyUsesFP(MI, MRI, TRI); })) {
       // Set the register bank of every operand to FPR.

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir?rev=368775&r1=368774&r2=368775&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir Tue Aug 13 16:51:20 2019
@@ -24,3 +24,27 @@ body:             |
     RET_ReallyLR implicit $x0
 
 ...
+---
+name:            unmerge_s128
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+frameInfo:
+  maxCallFrameSize: 0
+body:             |
+  bb.0:
+    liveins: $q0
+
+    ; s128 should be treated as an FPR/vector because it can't live on GPR bank.
+    ; CHECK-LABEL: name: unmerge_s128
+    ; CHECK: liveins: $q0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s128) = COPY $q0
+    ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](s128)
+    ; CHECK: $x0 = COPY [[UV]](s64)
+    ; CHECK: RET_ReallyLR implicit $x0
+    %0:_(s128) = COPY $q0
+    %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(s128)
+    $x0 = COPY %1(s64)
+    RET_ReallyLR implicit $x0
+
+...