[PATCH] D65929: [ARM] Make v2i1 a valid type for the MVE predicate register.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

It was the "buildvector" code from D65052 <https://reviews.llvm.org/D65052> that I was thinking of the most (or "buildvector" is what I've been calling it at least). How to get values into and out of v2i1 vectors, how to handle shuffles of i1's vectors, sign extending a v2i1 to a v2i64, that kind of thing.  The vectoriser will produce a lot of <2 x i1>'s in all kinds of weird and wonderful ways that we need to handle at least sensibly (if not always super efficiently, that's what cost models are for!).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65929/new/

https://reviews.llvm.org/D65929