[PATCH] D65887: [TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits for ISD::EXTRACT_VECTOR_ELT

Wed Aug 7 13:41:14 PDT 2019

tlively accepted this revision.
tlively added a comment.
This revision is now accepted and ready to land.

In D65887#1619471 <https://reviews.llvm.org/D65887#1619471>, @RKSimon wrote:

> @tlively Another thing we could consider is adding WebAssemblyISD opcodes for zero extending extract vector element - similar to what X86ISD does with PEXTRW/PEXTRB - this would avoid the need for the (and, extract_element(v, c), 0xFFFF) pattern that is causing all the problems.

Don't worry about bad shift codegen for now. We will actually be removing the scalarization of shifts entirely soon, since we were only ever scalarizing to get around a V8 bug with the shifts. I'll keep in mind the PEXTRW/PEXTRB example though, since I'm sure that pattern comes up elsewhere.

WebAssembly changes LGTM.

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  rL LLVM

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  https://reviews.llvm.org/D65887/new/

https://reviews.llvm.org/D65887