[PATCH] D65746: [ARM] Generate VHADDs/VHSUBs

[oliver cruickshank via Phabricator via llvm-commits]

oliverlars created this revision.
oliverlars added reviewers: t.p.northover, dmgreen, samparker, SjoerdMeijer, simon_tatham.
Herald added subscribers: kristof.beyls, javed.absar.
Herald added a project: LLVM.

This adds support for generating VHADDs (vector half add) and VHSUBs (vector half sub) from a VSHR (vector shift right) and VADD/VSUB (vector add/sub).

This is done from auto vectorising a loop with a pattern like C[i] = (A[i] + B[i])/2.

The instruction supports both signed and unsigned ints.


Repository:
  rL LLVM

https://reviews.llvm.org/D65746

Files:
  lib/Target/ARM/ARMInstrMVE.td
  test/CodeGen/Thumb2/mve-vhaddsub.ll

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