[PATCH] D65683: MVT: Add v3i16/v3f16 vectors

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: bogner, craig.topper, tpr, nhaehnle.
Herald added subscribers: aheejin, wdng, jvesely, dschuff.

AMDGPU has some buffer intrinsics which theoretically could use
this. Some of the generated tables include the 3 and 4 element vector
versions of these rounded to 64-bits, which is ambiguous. Add these to
help the table disambiguate these.

      

Assertion change is for the path odd sized vectors now take for R600.
v3i16 is widened to v4i16, which then needs to be promoted to v4i32.


https://reviews.llvm.org/D65683

Files:
  include/llvm/CodeGen/ValueTypes.td
  include/llvm/Support/MachineValueType.h
  lib/CodeGen/TargetLoweringBase.cpp
  lib/CodeGen/ValueTypes.cpp
  lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/X86/promote-vec3.ll
  test/CodeGen/X86/vec_cast.ll
  test/CodeGen/X86/widen_load-2.ll
  test/TableGen/intrinsic-varargs.td
  utils/TableGen/CodeGenTarget.cpp
  utils/TableGen/IntrinsicEmitter.cpp

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