[llvm] r367098 - [SelectionDAG] GetDemandedBits - update SIGN_EXTEND_INREG op to just call SimplifyMultipleUseDemandedBits.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 26 03:03:07 PDT 2019
Author: rksimon
Date: Fri Jul 26 03:03:07 2019
New Revision: 367098
URL: http://llvm.org/viewvc/llvm-project?rev=367098&view=rev
Log:
[SelectionDAG] GetDemandedBits - update SIGN_EXTEND_INREG op to just call SimplifyMultipleUseDemandedBits.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=367098&r1=367097&r2=367098&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jul 26 03:03:07 2019
@@ -2154,6 +2154,7 @@ SDValue SelectionDAG::GetDemandedBits(SD
}
case ISD::OR:
case ISD::XOR:
+ case ISD::SIGN_EXTEND_INREG:
return TLI->SimplifyMultipleUseDemandedBits(V, DemandedBits, DemandedElts,
*this, 0);
case ISD::SRL:
@@ -2199,15 +2200,6 @@ SDValue SelectionDAG::GetDemandedBits(SD
return getNode(ISD::ANY_EXTEND, SDLoc(V), V.getValueType(), DemandedSrc);
break;
}
- case ISD::SIGN_EXTEND_INREG:
- EVT ExVT = cast<VTSDNode>(V.getOperand(1))->getVT();
- unsigned ExVTBits = ExVT.getScalarSizeInBits();
-
- // If none of the extended bits are demanded, eliminate the sextinreg.
- if (DemandedBits.getActiveBits() <= ExVTBits)
- return V.getOperand(0);
-
- break;
}
return SDValue();
}
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