[PATCH] D63847: [MC] Add MCInstrAnalysis::evaluateMemoryOperandAddress

[Seiya Nuta via Phabricator via llvm-commits]

seiya updated this revision to Diff 211016.
seiya marked an inline comment as done.
seiya added a comment.

- Check that the segment register operand is not set.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63847/new/

https://reviews.llvm.org/D63847

Files:
  llvm/include/llvm/MC/MCInstrAnalysis.h
  llvm/lib/MC/MCInstrAnalysis.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp


Index: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
===================================================================
--- llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
@@ -399,6 +399,9 @@
   findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
                  uint64_t GotSectionVA,
                  const Triple &TargetTriple) const override;
+  Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
+                                                  uint64_t Addr,
+                                                  uint64_t Size) const override;
 };
 
 #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
@@ -511,7 +514,31 @@
       return findX86_64PltEntries(PltSectionVA, PltContents);
     default:
       return {};
-  }
+    }
+}
+
+Optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress(
+    const MCInst &Inst, uint64_t Addr, uint64_t Size) const {
+  MCInstrDesc Opcode = Info->get(Inst.getOpcode());
+  int MemOpStart = X86II::getMemoryOperandNo(Opcode.TSFlags);
+  if (MemOpStart == -1)
+    return None;
+  MemOpStart += X86II::getOperandBias(Opcode);
+
+  const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg);
+  const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);
+  const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg);
+  const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt);
+  const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp);
+  if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 ||
+      !Disp.isImm())
+    return None;
+
+  // RIP-relative addressing.
+  if (BaseReg.getReg() == X86::RIP)
+    return Addr + Size + Disp.getImm();
+
+  return None;
 }
 
 } // end of namespace X86_MC
Index: llvm/lib/MC/MCInstrAnalysis.cpp
===================================================================
--- llvm/lib/MC/MCInstrAnalysis.cpp
+++ llvm/lib/MC/MCInstrAnalysis.cpp
@@ -33,3 +33,9 @@
   Target = Addr+Size+Imm;
   return true;
 }
+
+Optional<uint64_t>
+MCInstrAnalysis::evaluateMemoryOperandAddress(const MCInst &Inst, uint64_t Addr,
+                                              uint64_t Size) const {
+  return None;
+}
Index: llvm/include/llvm/MC/MCInstrAnalysis.h
===================================================================
--- llvm/include/llvm/MC/MCInstrAnalysis.h
+++ llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -152,6 +152,12 @@
   evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
                  uint64_t &Target) const;
 
+  /// Given an instruction tries to get the address of a memory operand. Returns
+  /// the address on success.
+  virtual Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
+                                                          uint64_t Addr,
+                                                          uint64_t Size) const;
+
   /// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
   virtual std::vector<std::pair<uint64_t, uint64_t>>
   findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D63847.211016.patch
Type: text/x-patch
Size: 3187 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190722/a7455c49/attachment.bin>