[PATCH] D64953: GlobalISel: Support physical register inputs in patterns

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: dsanders, aemerson.
Herald added subscribers: Petar.Avramovic, kristof.beyls, tpr, javed.absar, rovka, nhaehnle, wdng, jvesely.

The current matchers seem to not like anonymous operands, so just use
the name of the register as a dummy name.

      

If the same name of the physical register is used, it treats them as
needing to be the same operand. I'm not sure if this is necessarily
useful or makes any sense. It may be a useful behavior for tied
operands?

      

I'm also not sure if this should verify the register bank of the input
matches the physical register class. This doesn't work on AMDGPU as-is
because it fails to find the registser class for M0 for some reason,
and for wzr on AArch64.


https://reviews.llvm.org/D64953

Files:
  include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
  test/TableGen/gisel-physreg-input.td
  utils/TableGen/GlobalISelEmitter.cpp

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