[llvm] r366505 - [AMDGPU] Drop Reg32 and use regular AsmName
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 18 15:18:33 PDT 2019
Author: rampitec
Date: Thu Jul 18 15:18:33 2019
New Revision: 366505
URL: http://llvm.org/viewvc/llvm-project?rev=366505&view=rev
Log:
[AMDGPU] Drop Reg32 and use regular AsmName
This allows to reduce generated AMDGPUGenAsmWriter.inc by ~100Kb.
Differential Revision: https://reviews.llvm.org/D64952
Modified:
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp?rev=366505&r1=366504&r2=366505&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp Thu Jul 18 15:18:33 2019
@@ -292,7 +292,7 @@ void AMDGPUInstPrinter::printRegOperand(
}
#endif
- unsigned AltName = AMDGPU::Reg32;
+ unsigned AltName = AMDGPU::NoRegAltName;
if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(RegNo) ||
MRI.getRegClass(AMDGPU::SGPR_64RegClassID).contains(RegNo) ||
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=366505&r1=366504&r2=366505&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Thu Jul 18 15:18:33 2019
@@ -1352,7 +1352,6 @@ StringRef SIRegisterInfo::getRegAsmName(
unsigned AltName = AMDGPU::NoRegAltName;
switch (Size) {
- case 32: AltName = AMDGPU::Reg32; break;
case 64: AltName = AMDGPU::Reg64; break;
case 96: AltName = AMDGPU::Reg96; break;
case 128: AltName = AMDGPU::Reg128; break;
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td?rev=366505&r1=366504&r2=366505&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td Thu Jul 18 15:18:33 2019
@@ -39,7 +39,6 @@ class getSubRegs<int size> {
let Namespace = "AMDGPU" in {
defset list<RegAltNameIndex> AllRegAltNameIndices = {
- def Reg32 : RegAltNameIndex;
def Reg64 : RegAltNameIndex;
def Reg96 : RegAltNameIndex;
def Reg128 : RegAltNameIndex;
@@ -56,9 +55,8 @@ defset list<RegAltNameIndex> AllRegAltNa
class SIReg <string n, bits<16> regIdx = 0, string prefix = "",
int regNo = !cast<int>(regIdx)> :
Register<n, !if(!eq(prefix, ""),
- [ n, n, n, n, n, n, n, n ],
- [ prefix # regNo,
- prefix # "[" # regNo # ":" # !and(!add(regNo, 1), 255) # "]",
+ [ n, n, n, n, n, n, n ],
+ [ prefix # "[" # regNo # ":" # !and(!add(regNo, 1), 255) # "]",
prefix # "[" # regNo # ":" # !and(!add(regNo, 2), 255) # "]",
prefix # "[" # regNo # ":" # !and(!add(regNo, 3), 255) # "]",
prefix # "[" # regNo # ":" # !and(!add(regNo, 4), 255) # "]",
@@ -78,7 +76,7 @@ class SIReg <string n, bits<16> regIdx =
class SIRegisterWithSubRegs<string n, list<Register> subregs> :
RegisterWithSubRegs<n, subregs> {
let RegAltNameIndices = AllRegAltNameIndices;
- let AltNames = [ n, n, n, n, n, n, n, n ];
+ let AltNames = [ n, n, n, n, n, n, n ];
}
// Special Registers
@@ -191,19 +189,19 @@ def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT
// SGPR registers
foreach Index = 0-105 in {
- def SGPR#Index : SIReg <"SGPR"#Index, Index, "s">;
+ def SGPR#Index : SIReg <"s"#Index, Index, "s">;
}
// VGPR registers
foreach Index = 0-255 in {
- def VGPR#Index : SIReg <"VGPR"#Index, Index, "v"> {
+ def VGPR#Index : SIReg <"v"#Index, Index, "v"> {
let HWEncoding{8} = 1;
}
}
// AccVGPR registers
foreach Index = 0-255 in {
- def AGPR#Index : SIReg <"AGPR"#Index, Index, "a"> {
+ def AGPR#Index : SIReg <"a"#Index, Index, "a"> {
let HWEncoding{8} = 1;
}
}
@@ -226,7 +224,7 @@ def M0_CLASS : RegisterClass<"AMDGPU", [
// SGPR 32-bit registers
def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
- (add (sequence "SGPR%u", 0, 105)), Reg32> {
+ (add (sequence "SGPR%u", 0, 105))> {
// Give all SGPR classes higher priority than VGPR classes, because
// we want to spill SGPRs to VGPRs.
let AllocationPriority = 9;
@@ -451,7 +449,7 @@ def TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_
// VGPR 32-bit registers
// i16/f16 only on VI+
def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
- (add (sequence "VGPR%u", 0, 255)), Reg32> {
+ (add (sequence "VGPR%u", 0, 255))> {
let AllocationPriority = 1;
let Size = 32;
}
@@ -549,7 +547,7 @@ def VGPR_1024 : RegisterTuples<getSubReg
// AccVGPR 32-bit registers
def AGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
- (add (sequence "AGPR%u", 0, 255)), Reg32> {
+ (add (sequence "AGPR%u", 0, 255))> {
let AllocationPriority = 1;
let Size = 32;
}
@@ -625,7 +623,7 @@ def AGPR_1024 : RegisterTuples<getSubReg
//===----------------------------------------------------------------------===//
def Pseudo_SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
- (add FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG), Reg32> {
+ (add FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG)> {
let isAllocatable = 0;
let CopyCost = -1;
}
@@ -637,7 +635,7 @@ def Pseudo_SReg_128 : RegisterClass<"AMD
}
def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
- (add LDS_DIRECT), Reg32> {
+ (add LDS_DIRECT)> {
let isAllocatable = 0;
let CopyCost = -1;
}
@@ -648,29 +646,28 @@ def SReg_32_XM0_XEXEC : RegisterClass<"A
(add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI,
SGPR_NULL, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,
SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID,
- SRC_VCCZ, SRC_EXECZ, SRC_SCC), Reg32> {
+ SRC_VCCZ, SRC_EXECZ, SRC_SCC)> {
let AllocationPriority = 10;
}
def SReg_32_XEXEC_HI : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
- (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS), Reg32> {
+ (add SReg_32_XM0_XEXEC, EXEC_LO, M0_CLASS)> {
let AllocationPriority = 10;
}
def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
- (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI), Reg32> {
+ (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> {
let AllocationPriority = 10;
}
// Register class for all scalar registers (SGPRs + Special Registers)
def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
- (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI), Reg32> {
+ (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI)> {
let AllocationPriority = 10;
}
def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32,
- (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI, LDS_DIRECT_CLASS),
- Reg32> {
+ (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI, LDS_DIRECT_CLASS)> {
let isAllocatable = 0;
}
@@ -794,7 +791,7 @@ def SReg_512 : RegisterClass<"AMDGPU", [
}
def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
- (add VGPR_32, LDS_DIRECT_CLASS), Reg32> {
+ (add VGPR_32, LDS_DIRECT_CLASS)> {
let isAllocatable = 0;
}
@@ -897,12 +894,12 @@ def AReg_1024 : RegisterClass<"AMDGPU",
let AllocationPriority = 8;
}
-def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32), Reg32> {
+def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
let Size = 32;
}
def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
- (add VGPR_32, SReg_32, LDS_DIRECT_CLASS), Reg32> {
+ (add VGPR_32, SReg_32, LDS_DIRECT_CLASS)> {
let isAllocatable = 0;
}
@@ -912,7 +909,7 @@ def VS_64 : RegisterClass<"AMDGPU", [i64
}
def AV_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
- (add AGPR_32, VGPR_32), Reg32> {
+ (add AGPR_32, VGPR_32)> {
let isAllocatable = 0;
}
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