[llvm] r366302 - [mips] Name inline asm constraint test cases in a uniform manner. NFC
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 17 01:11:57 PDT 2019
Author: atanasyan
Date: Wed Jul 17 01:11:57 2019
New Revision: 366302
URL: http://llvm.org/viewvc/llvm-project?rev=366302&view=rev
Log:
[mips] Name inline asm constraint test cases in a uniform manner. NFC
Added:
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-R.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-l1.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-i1.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-m-1.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-m-2.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-o.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-reg.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint.ll
Removed:
llvm/trunk/test/CodeGen/Mips/inline-asm-i-constraint-i1.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
llvm/trunk/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll
llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll
llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_R.ll
llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_ZC.ll
llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_m.ll
llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_o.ll
llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
Removed: llvm/trunk/test/CodeGen/Mips/inline-asm-i-constraint-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inline-asm-i-constraint-i1.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inline-asm-i-constraint-i1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inline-asm-i-constraint-i1.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc -mtriple=mips64el-unknown-linux-gnu < %s | FileCheck %s
-
-; Make sure that boolean immediates are properly (zero) extended.
-; CHECK: TEST 42 + 1 - .
-
-target triple = "mips64el-unknown-linux-gnu"
-
-define i32 @foo() #0 {
-entry:
- tail call void asm sideeffect "#TEST 42 + ${0:c} - .\0A\09", "i,~{dirflag},~{fpsr},~{flags}"(i1 true) #0
- ret i32 1
-}
-
-attributes #0 = { nounwind }
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-I-1.ll (removed)
@@ -1,15 +0,0 @@
-;
-;This is a negative test. The constant value given for the constraint
-;is greater than 16 bits.
-;
-; RUN: not llc -march=mipsel < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-define i32 @main() nounwind {
-entry:
-
-;CHECK-ERRORS: error: invalid operand for inline asm constraint 'I'
- tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 1048576) nounwind
- ret i32 0
-}
-
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-J.ll (removed)
@@ -1,16 +0,0 @@
-;
-;This is a negative test. The constant value given for the constraint (J)
-;is non-zero (3).
-;
-; RUN: not llc -march=mipsel < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-define i32 @main() nounwind {
-entry:
-
-;CHECK-ERRORS: error: invalid operand for inline asm constraint 'J'
-
- tail call i32 asm "addiu $0,$1,$2", "=r,r,J"(i32 1024, i32 3) nounwind
- ret i32 0
-}
-
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-K.ll (removed)
@@ -1,16 +0,0 @@
-;
-;This is a negative test. The constant value given for the constraint (K)
-;is greater than 16 bits (0x00100000).
-;
-; RUN: not llc -march=mipsel < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-define i32 @main() nounwind {
-entry:
-
-;CHECK-ERRORS: error: invalid operand for inline asm constraint 'K'
-
- tail call i32 asm "addu $0,$1,$2", "=r,r,K"(i32 1024, i32 1048576) nounwind
- ret i32 0
-}
-
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-L.ll (removed)
@@ -1,16 +0,0 @@
-;
-;This is a negative test. The constant value given for the constraint (L)
-;is non-zero in the lower 16 bits (0x00100003).
-;
-; RUN: not llc -march=mipsel < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-define i32 @main() nounwind {
-entry:
-
-;CHECK-ERRORS: error: invalid operand for inline asm constraint 'L'
-
- tail call i32 asm "addiu $0,$1,$2", "=r,r,L"(i32 7, i32 1048579) nounwind
- ret i32 0
-}
-
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-N.ll (removed)
@@ -1,17 +0,0 @@
-
-;This is a negative test. The constant value given for the constraint (N).
-;immediate in the range of -65535 to -1 (inclusive).
-;Our example uses the positive value 3.
-;
-; RUN: not llc -march=mipsel < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-define i32 @main() nounwind {
-entry:
-
-;CHECK-ERRORS: error: invalid operand for inline asm constraint 'N'
-
- tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 3) nounwind
- ret i32 0
-}
-
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-O.ll (removed)
@@ -1,16 +0,0 @@
-;
-;This is a negative test. The constant value given for the constraint (O).
-;signed 15 bit immediate (+- 16383).
-;Our example uses the positive value 16384.
-;
-; RUN: not llc -march=mipsel < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-define i32 @main() nounwind {
-entry:
-
-;CHECK-ERRORS: error: invalid operand for inline asm constraint 'O'
-
- tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 undef, i32 16384) nounwind
- ret i32 0
-}
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-P.ll (removed)
@@ -1,16 +0,0 @@
-;
-; This is a negative test. The constant value given for the constraint (P).
-; A constant in the range of 1 to 655535 inclusive.
-; Our example uses the positive value 655536.
-;
-; RUN: not llc -march=mipsel < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-define i32 @main() nounwind {
-entry:
-
-;CHECK-ERRORS: error: invalid operand for inline asm constraint 'P'
-
- tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,P"(i32 undef, i32 655536) nounwind
- ret i32 0
-}
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll (removed)
@@ -1,13 +0,0 @@
-; Negative test. The constraint 'l' represents the register 'lo'.
-; Check error message in case of invalid usage.
-;
-; RUN: not llc -march=mips -filetype=obj < %s 2>&1 | FileCheck %s
-
-define void @constraint_l() nounwind {
-entry:
-
-; CHECK: error: invalid operand for instruction
-
- tail call i16 asm sideeffect "addiu $0,$1,$2", "=l,r,r,~{$1}"(i16 0, i16 0)
- ret void
-}
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll (removed)
@@ -1,55 +0,0 @@
-; Positive test for inline register constraints
-;
-; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
-; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
-
-define i32 @main() nounwind {
-entry:
-
-; r with char
-;CHECK: #APP
-;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23
-;CHECK: #NO_APP
- tail call i8 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i8 27, i8 23) nounwind
-
-; r with short
-;CHECK: #APP
-;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 13
-;CHECK: #NO_APP
- tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i16 17, i16 13) nounwind
-
-; r with int
-;CHECK: #APP
-;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
-;CHECK: #NO_APP
- tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i32 7, i32 3) nounwind
-
-; Now c with 1024: make sure register $25 is picked
-; CHECK: #APP
-; CHECK: addiu $25, ${{[0-9]+}}, 1024
-; CHECK: #NO_APP
- tail call i32 asm sideeffect "addiu $0, $1, $2", "=c,c,I"(i32 4194304, i32 1024) nounwind
-
-; Now l with 1024: make sure register lo is picked. We do this by checking the instruction
-; after the inline expression for a mflo to pull the value out of lo.
-; CHECK: #APP
-; CHECK: mtlo ${{[0-9]+}}
-; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}
-; CHECK: #NO_APP
-; CHECK-NEXT: mflo ${{[0-9]+}}
- %bosco = alloca i32, align 4
- call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
- store volatile i32 %4, i32* %bosco, align 4
-
-; Check the 'l' constraint for 16-bit type.
-; CHECK: #APP
-; CHECK: mtlo ${{[0-9]+}}
-; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}
-; CHECK: #NO_APP
-; CHECK-NEXT: mflo ${{[0-9]+}}
- %bosco16 = alloca i16, align 4
- call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
- store volatile i16 %5, i16* %bosco16, align 4
-
- ret i32 0
-}
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll (removed)
@@ -1,20 +0,0 @@
-;
-; Register constraint "r" shouldn't take long long unless
-; The target is 64 bit.
-;
-;
-; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
-
-
-define i32 @main() nounwind {
-entry:
-
-
-; r with long long
-;CHECK: #APP
-;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
-;CHECK: #NO_APP
- tail call i64 asm sideeffect "addiu $0, $1, $2", "=r,r,i"(i64 7, i64 3) nounwind
- ret i32 0
-}
-
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-R.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-R.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-R.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-R.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,60 @@
+; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+
+ at data = global [8193 x i32] zeroinitializer
+
+define void @R(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: R:
+
+ call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
+
+ ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 0($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @R_offset_4(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: R_offset_4:
+
+ call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
+
+ ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 4($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @R_offset_254(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: R_offset_254:
+
+ call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 63))
+
+ ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 252($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @R_offset_256(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: R_offset_256:
+
+ call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 64))
+
+ ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
+ ; CHECK: #APP
+ ; CHECK: lw $1, 0($[[BASEPTR2]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-ZC-1.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,167 @@
+; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,09BIT
+; RUN: llc -march=mipsel -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,12BIT
+; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,16BIT
+
+ at data = global [8193 x i32] zeroinitializer
+
+define void @ZC(i32 *%p) nounwind {
+entry:
+ ; ALL-LABEL: ZC:
+
+ call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
+
+ ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; ALL: #APP
+ ; ALL: lw $1, 0($[[BASEPTR]])
+ ; ALL: #NO_APP
+
+ ret void
+}
+
+define void @ZC_offset_n4(i32 *%p) nounwind {
+entry:
+ ; ALL-LABEL: ZC_offset_n4:
+
+ call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 -1))
+
+ ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; ALL: #APP
+ ; ALL: lw $1, -4($[[BASEPTR]])
+ ; ALL: #NO_APP
+
+ ret void
+}
+
+define void @ZC_offset_4(i32 *%p) nounwind {
+entry:
+ ; ALL-LABEL: ZC_offset_4:
+
+ call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
+
+ ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; ALL: #APP
+ ; ALL: lw $1, 4($[[BASEPTR]])
+ ; ALL: #NO_APP
+
+ ret void
+}
+
+define void @ZC_offset_252(i32 *%p) nounwind {
+entry:
+ ; ALL-LABEL: ZC_offset_252:
+
+ call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 63))
+
+ ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; ALL: #APP
+ ; ALL: lw $1, 252($[[BASEPTR]])
+ ; ALL: #NO_APP
+
+ ret void
+}
+
+define void @ZC_offset_256(i32 *%p) nounwind {
+entry:
+ ; ALL-LABEL: ZC_offset_256:
+
+ call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 64))
+
+ ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+
+ ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
+
+ ; ALL: #APP
+
+ ; 09BIT: lw $1, 0($[[BASEPTR2]])
+ ; 12BIT: lw $1, 256($[[BASEPTR]])
+ ; 16BIT: lw $1, 256($[[BASEPTR]])
+
+ ; ALL: #NO_APP
+
+ ret void
+}
+
+define void @ZC_offset_2044(i32 *%p) nounwind {
+entry:
+ ; ALL-LABEL: ZC_offset_2044:
+
+ call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 511))
+
+ ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+
+ ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 2044
+
+ ; ALL: #APP
+
+ ; 09BIT: lw $1, 0($[[BASEPTR2]])
+ ; 12BIT: lw $1, 2044($[[BASEPTR]])
+ ; 16BIT: lw $1, 2044($[[BASEPTR]])
+
+ ; ALL: #NO_APP
+
+ ret void
+}
+
+define void @ZC_offset_2048(i32 *%p) nounwind {
+entry:
+ ; ALL-LABEL: ZC_offset_2048:
+
+ call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 512))
+
+ ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
+
+ ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 2048
+ ; 12BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 2048
+
+ ; ALL: #APP
+
+ ; 09BIT: lw $1, 0($[[BASEPTR2]])
+ ; 12BIT: lw $1, 0($[[BASEPTR2]])
+ ; 16BIT: lw $1, 2048($[[BASEPTR]])
+
+ ; ALL: #NO_APP
+
+ ret void
+}
+
+define void @ZC_offset_32764(i32 *%p) nounwind {
+entry:
+ ; ALL-LABEL: ZC_offset_32764:
+
+ call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8191))
+
+ ; ALL-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+
+ ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 32764
+ ; 12BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 32764
+
+ ; ALL: #APP
+
+ ; 09BIT: lw $1, 0($[[BASEPTR2]])
+ ; 12BIT: lw $1, 0($[[BASEPTR2]])
+ ; 16BIT: lw $1, 32764($[[BASEPTR]])
+
+ ; ALL: #NO_APP
+
+ ret void
+}
+
+define void @ZC_offset_32768(i32 *%p) nounwind {
+entry:
+ ; ALL-LABEL: ZC_offset_32768:
+
+ call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8192))
+
+ ; ALL-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; ALL-DAG: ori $[[T0:[0-9]+]], $zero, 32768
+
+ ; 09BIT: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
+ ; 12BIT: addu16 $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
+ ; 16BIT: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
+
+ ; ALL: #APP
+ ; ALL: lw $1, 0($[[BASEPTR2]])
+ ; ALL: #NO_APP
+
+ ret void
+}
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-ZC-2.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,38 @@
+; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s --check-prefixes=ALL,R6
+; RUN: llc -march=mips -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic \
+; RUN: < %s | FileCheck %s --check-prefixes=ALL,R6
+; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,PRER6
+; RUN: llc -march=mips -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
+; RUN: < %s | FileCheck %s --check-prefixes=ALL,PRER6
+
+
+%struct.anon = type { [63 x i32], i32, i32 }
+
+define i32 @Atomic() {
+; CHECK-LABEL: Atomic:
+entry:
+ %s = alloca %struct.anon, align 4
+ %0 = bitcast %struct.anon* %s to i8*
+ %count = getelementptr inbounds %struct.anon, %struct.anon* %s, i64 0, i32 1
+ store i32 0, i32* %count, align 4
+; R6: addiu $[[R0:[0-9a-z]+]], $sp, {{[0-9]+}}
+
+; ALL: #APP
+
+; R6: ll ${{[0-9a-z]+}}, 0($[[R0]])
+; R6: sc ${{[0-9a-z]+}}, 0($[[R0]])
+
+; PRER6: ll ${{[0-9a-z]+}}, {{[0-9]+}}(${{[0-9a-z]+}})
+; PRER6: sc ${{[0-9a-z]+}}, {{[0-9]+}}(${{[0-9a-z]+}})
+
+; ALL: #NO_APP
+
+ %1 = call { i32, i32 } asm sideeffect ".set push\0A.set noreorder\0A1:\0All $0, $2\0Aaddu $1, $0, $3\0Asc $1, $2\0Abeqz $1, 1b\0Aaddu $1, $0, $3\0A.set pop\0A", "=&r,=&r,=*^ZC,Ir,*^ZC,~{memory},~{$1}"(i32* %count, i32 10, i32* %count)
+ %asmresult1.i = extractvalue { i32, i32 } %1, 1
+ %cmp = icmp ne i32 %asmresult1.i, 10
+ %conv = zext i1 %cmp to i32
+ %call2 = call i32 @f(i32 signext %conv)
+ ret i32 %call2
+}
+
+declare i32 @f(i32 signext)
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-I-1.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,15 @@
+;
+;This is a negative test. The constant value given for the constraint
+;is greater than 16 bits.
+;
+; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+define i32 @main() nounwind {
+entry:
+
+;CHECK-ERRORS: error: invalid operand for inline asm constraint 'I'
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 1048576) nounwind
+ ret i32 0
+}
+
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-J.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,16 @@
+;
+;This is a negative test. The constant value given for the constraint (J)
+;is non-zero (3).
+;
+; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+define i32 @main() nounwind {
+entry:
+
+;CHECK-ERRORS: error: invalid operand for inline asm constraint 'J'
+
+ tail call i32 asm "addiu $0,$1,$2", "=r,r,J"(i32 1024, i32 3) nounwind
+ ret i32 0
+}
+
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-K.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,16 @@
+;
+;This is a negative test. The constant value given for the constraint (K)
+;is greater than 16 bits (0x00100000).
+;
+; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+define i32 @main() nounwind {
+entry:
+
+;CHECK-ERRORS: error: invalid operand for inline asm constraint 'K'
+
+ tail call i32 asm "addu $0,$1,$2", "=r,r,K"(i32 1024, i32 1048576) nounwind
+ ret i32 0
+}
+
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-L.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,16 @@
+;
+;This is a negative test. The constant value given for the constraint (L)
+;is non-zero in the lower 16 bits (0x00100003).
+;
+; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+define i32 @main() nounwind {
+entry:
+
+;CHECK-ERRORS: error: invalid operand for inline asm constraint 'L'
+
+ tail call i32 asm "addiu $0,$1,$2", "=r,r,L"(i32 7, i32 1048579) nounwind
+ ret i32 0
+}
+
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-N.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,17 @@
+
+;This is a negative test. The constant value given for the constraint (N).
+;immediate in the range of -65535 to -1 (inclusive).
+;Our example uses the positive value 3.
+;
+; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+define i32 @main() nounwind {
+entry:
+
+;CHECK-ERRORS: error: invalid operand for inline asm constraint 'N'
+
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 3) nounwind
+ ret i32 0
+}
+
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-O.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,16 @@
+;
+;This is a negative test. The constant value given for the constraint (O).
+;signed 15 bit immediate (+- 16383).
+;Our example uses the positive value 16384.
+;
+; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+define i32 @main() nounwind {
+entry:
+
+;CHECK-ERRORS: error: invalid operand for inline asm constraint 'O'
+
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 undef, i32 16384) nounwind
+ ret i32 0
+}
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-P.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,16 @@
+;
+; This is a negative test. The constant value given for the constraint (P).
+; A constant in the range of 1 to 655535 inclusive.
+; Our example uses the positive value 655536.
+;
+; RUN: not llc -march=mipsel < %s 2> %t
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+define i32 @main() nounwind {
+entry:
+
+;CHECK-ERRORS: error: invalid operand for inline asm constraint 'P'
+
+ tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,P"(i32 undef, i32 655536) nounwind
+ ret i32 0
+}
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-l1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-l1.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-l1.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-bad-l1.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,13 @@
+; Negative test. The constraint 'l' represents the register 'lo'.
+; Check error message in case of invalid usage.
+;
+; RUN: not llc -march=mips -filetype=obj < %s 2>&1 | FileCheck %s
+
+define void @constraint_l() nounwind {
+entry:
+
+; CHECK: error: invalid operand for instruction
+
+ tail call i16 asm sideeffect "addiu $0,$1,$2", "=l,r,r,~{$1}"(i16 0, i16 0)
+ ret void
+}
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-i1.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-i1.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-i1.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=mips64el-unknown-linux-gnu < %s | FileCheck %s
+
+; Make sure that boolean immediates are properly (zero) extended.
+; CHECK: TEST 42 + 1 - .
+
+target triple = "mips64el-unknown-linux-gnu"
+
+define i32 @foo() #0 {
+entry:
+ tail call void asm sideeffect "#TEST 42 + ${0:c} - .\0A\09", "i,~{dirflag},~{fpsr},~{flags}"(i1 true) #0
+ ret i32 1
+}
+
+attributes #0 = { nounwind }
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-m-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-m-1.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-m-1.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-m-1.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,61 @@
+; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+
+ at data = global [8193 x i32] zeroinitializer
+
+define void @m(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: m:
+
+ call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
+
+ ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 0($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @m_offset_4(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: m_offset_4:
+
+ call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
+
+ ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 4($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @m_offset_32764(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: m_offset_32764:
+
+ call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8191))
+
+ ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 32764($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @m_offset_32768(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: m_offset_32768:
+
+ call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8192))
+
+ ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK-DAG: ori $[[T0:[0-9]+]], $zero, 32768
+ ; CHECK: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
+ ; CHECK: #APP
+ ; CHECK: lw $1, 0($[[BASEPTR2]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-m-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-m-2.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-m-2.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-m-2.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,67 @@
+; RUN: llc -march=mips -relocation-model=pic < %s \
+; RUN: | FileCheck --check-prefixes=CHECK,EB %s
+; RUN: llc -march=mipsel -relocation-model=pic < %s \
+; RUN: | FileCheck --check-prefixes=CHECK,EL %s
+
+; Simple memory
+ at g1 = external global i32
+
+define i32 @f1(i32 %x) nounwind {
+entry:
+; CHECK-LABEL: f1:
+; CHECK: #APP
+; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp)
+; CHECK: #NO_APP
+; CHECK: lw $[[T1:[0-9]+]], %got(g1)
+; CHECK: #APP
+; CHECK: lw $[[T3:[0-9]+]], [[OFFSET]]($sp)
+; CHECK: #NO_APP
+; CHECK: sw $[[T3]], 0($[[T1]])
+
+ %l1 = alloca i32, align 4
+ call void asm "sw $1, $0", "=*m,r"(i32* %l1, i32 %x) nounwind
+ %0 = call i32 asm "lw $0, $1", "=r,*m"(i32* %l1) nounwind
+ store i32 %0, i32* @g1, align 4
+ ret i32 %0
+}
+
+; CHECK-LABEL: main:
+; "D": Second word of a double word. This works for any memory element
+; double or single.
+; CHECK: #APP
+; CHECK: lw ${{[0-9]+}}, 16(${{[0-9]+}})
+; CHECK: #NO_APP
+
+; No "D": First word of a double word. This works for any memory element
+; double or single.
+; CHECK: #APP
+; CHECK: lw ${{[0-9]+}}, 12(${{[0-9]+}})
+; CHECK: #NO_APP
+
+; "M": High-order word of a double word.
+; CHECK: #APP
+; EB: lw ${{[0-9]+}}, 12(${{[0-9]+}})
+; EL: lw ${{[0-9]+}}, 16(${{[0-9]+}})
+; CHECK: #NO_APP
+
+; "L": Low-order word of a double word.
+; CHECK: #APP
+; EB: lw ${{[0-9]+}}, 16(${{[0-9]+}})
+; EL: lw ${{[0-9]+}}, 12(${{[0-9]+}})
+; CHECK: #NO_APP
+
+ at b = common global [20 x i32] zeroinitializer, align 4
+
+define void @main() {
+entry:
+; Second word:
+ tail call void asm sideeffect " lw $0, ${1:D}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
+; First word. Notice, no 'D':
+ tail call void asm sideeffect " lw $0, ${1}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
+
+; High-order part.
+ tail call void asm sideeffect " lw $0, ${1:M}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
+; Low-order part.
+ tail call void asm sideeffect " lw $0, ${1:L}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
+ ret void
+}
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-o.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-o.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-o.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-o.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,61 @@
+; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
+
+ at data = global [8193 x i32] zeroinitializer
+
+define void @o(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: o:
+
+ call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
+
+ ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 0($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @o_offset_4(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: o_offset_4:
+
+ call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
+
+ ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 4($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @o_offset_32764(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: o_offset_32764:
+
+ call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8191))
+
+ ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK: #APP
+ ; CHECK: lw $1, 32764($[[BASEPTR]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
+
+define void @o_offset_32768(i32 *%p) nounwind {
+entry:
+ ; CHECK-LABEL: o_offset_32768:
+
+ call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8192))
+
+ ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
+ ; CHECK-DAG: ori $[[T0:[0-9]+]], $zero, 32768
+ ; CHECK: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
+ ; CHECK: #APP
+ ; CHECK: lw $1, 0($[[BASEPTR2]])
+ ; CHECK: #NO_APP
+
+ ret void
+}
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-reg.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-reg.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-reg.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,55 @@
+; Positive test for inline register constraints
+;
+; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
+
+define i32 @main() nounwind {
+entry:
+
+; r with char
+;CHECK: #APP
+;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23
+;CHECK: #NO_APP
+ tail call i8 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i8 27, i8 23) nounwind
+
+; r with short
+;CHECK: #APP
+;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 13
+;CHECK: #NO_APP
+ tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i16 17, i16 13) nounwind
+
+; r with int
+;CHECK: #APP
+;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
+;CHECK: #NO_APP
+ tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i32 7, i32 3) nounwind
+
+; Now c with 1024: make sure register $25 is picked
+; CHECK: #APP
+; CHECK: addiu $25, ${{[0-9]+}}, 1024
+; CHECK: #NO_APP
+ tail call i32 asm sideeffect "addiu $0, $1, $2", "=c,c,I"(i32 4194304, i32 1024) nounwind
+
+; Now l with 1024: make sure register lo is picked. We do this by checking the instruction
+; after the inline expression for a mflo to pull the value out of lo.
+; CHECK: #APP
+; CHECK: mtlo ${{[0-9]+}}
+; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK: #NO_APP
+; CHECK-NEXT: mflo ${{[0-9]+}}
+ %bosco = alloca i32, align 4
+ call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
+ store volatile i32 %4, i32* %bosco, align 4
+
+; Check the 'l' constraint for 16-bit type.
+; CHECK: #APP
+; CHECK: mtlo ${{[0-9]+}}
+; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK: #NO_APP
+; CHECK-NEXT: mflo ${{[0-9]+}}
+ %bosco16 = alloca i16, align 4
+ call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
+ store volatile i16 %5, i16* %bosco16, align 4
+
+ ret i32 0
+}
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-reg64.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-reg64.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint-reg64.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,20 @@
+;
+; Register constraint "r" shouldn't take long long unless
+; The target is 64 bit.
+;
+;
+; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
+
+
+define i32 @main() nounwind {
+entry:
+
+
+; r with long long
+;CHECK: #APP
+;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
+;CHECK: #NO_APP
+ tail call i64 asm sideeffect "addiu $0, $1, $2", "=r,r,i"(i64 7, i64 3) nounwind
+ ret i32 0
+}
+
Added: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint.ll?rev=366302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint.ll Wed Jul 17 01:11:57 2019
@@ -0,0 +1,75 @@
+; RUN: llc -no-integrated-as -march=mipsel < %s | \
+; RUN: FileCheck %s -check-prefixes=ALL,GAS
+; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefixes=ALL,IAS
+
+define void @constraint_I() nounwind {
+; First I with short
+; ALL-LABEL: constraint_I:
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 4096
+; ALL: #NO_APP
+ tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i16 7, i16 4096) nounwind
+
+; Then I with int
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
+; ALL: #NO_APP
+ tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i32 7, i32 -3) nounwind
+ ret void
+}
+
+define void @constraint_J() nounwind {
+; Now J with 0
+; ALL-LABEL: constraint_J:
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0
+; ALL: #NO_APP
+ tail call i32 asm sideeffect "addiu $0, $1, $2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
+ ret void
+}
+
+define void @constraint_K() nounwind {
+; Now K with 64
+; ALL: #APP
+; GAS: addu ${{[0-9]+}}, ${{[0-9]+}}, 64
+; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 64
+; ALL: #NO_APP
+ tail call i16 asm sideeffect "addu $0, $1, $2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind
+ ret void
+}
+
+define void @constraint_L() nounwind {
+; Now L with 0x00100000
+; ALL: #APP
+; ALL: add ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; ALL: #NO_APP
+ tail call i32 asm sideeffect "add $0, $1, $3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind
+ ret void
+}
+
+define void @constraint_N() nounwind {
+; Now N with -3
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
+; ALL: #NO_APP
+ tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,N"(i32 7, i32 -3) nounwind
+ ret void
+}
+
+define void @constraint_O() nounwind {
+; Now O with -3
+; ALL: #APP
+; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
+; ALL: #NO_APP
+ tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,O"(i32 7, i16 -3) nounwind
+ ret void
+}
+
+define void @constraint_P() nounwind {
+; Now P with 65535
+; ALL: #APP
+; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 65535
+; ALL: #NO_APP
+ tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,P"(i32 7, i32 65535) nounwind
+ ret void
+}
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll (removed)
@@ -1,38 +0,0 @@
-; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s --check-prefixes=ALL,R6
-; RUN: llc -march=mips -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic \
-; RUN: < %s | FileCheck %s --check-prefixes=ALL,R6
-; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,PRER6
-; RUN: llc -march=mips -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
-; RUN: < %s | FileCheck %s --check-prefixes=ALL,PRER6
-
-
-%struct.anon = type { [63 x i32], i32, i32 }
-
-define i32 @Atomic() {
-; CHECK-LABEL: Atomic:
-entry:
- %s = alloca %struct.anon, align 4
- %0 = bitcast %struct.anon* %s to i8*
- %count = getelementptr inbounds %struct.anon, %struct.anon* %s, i64 0, i32 1
- store i32 0, i32* %count, align 4
-; R6: addiu $[[R0:[0-9a-z]+]], $sp, {{[0-9]+}}
-
-; ALL: #APP
-
-; R6: ll ${{[0-9a-z]+}}, 0($[[R0]])
-; R6: sc ${{[0-9a-z]+}}, 0($[[R0]])
-
-; PRER6: ll ${{[0-9a-z]+}}, {{[0-9]+}}(${{[0-9a-z]+}})
-; PRER6: sc ${{[0-9a-z]+}}, {{[0-9]+}}(${{[0-9a-z]+}})
-
-; ALL: #NO_APP
-
- %1 = call { i32, i32 } asm sideeffect ".set push\0A.set noreorder\0A1:\0All $0, $2\0Aaddu $1, $0, $3\0Asc $1, $2\0Abeqz $1, 1b\0Aaddu $1, $0, $3\0A.set pop\0A", "=&r,=&r,=*^ZC,Ir,*^ZC,~{memory},~{$1}"(i32* %count, i32 10, i32* %count)
- %asmresult1.i = extractvalue { i32, i32 } %1, 1
- %cmp = icmp ne i32 %asmresult1.i, 10
- %conv = zext i1 %cmp to i32
- %call2 = call i32 @f(i32 signext %conv)
- ret i32 %call2
-}
-
-declare i32 @f(i32 signext)
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm_constraint.ll (removed)
@@ -1,75 +0,0 @@
-; RUN: llc -no-integrated-as -march=mipsel < %s | \
-; RUN: FileCheck %s -check-prefixes=ALL,GAS
-; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefixes=ALL,IAS
-
-define void @constraint_I() nounwind {
-; First I with short
-; ALL-LABEL: constraint_I:
-; ALL: #APP
-; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 4096
-; ALL: #NO_APP
- tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i16 7, i16 4096) nounwind
-
-; Then I with int
-; ALL: #APP
-; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
-; ALL: #NO_APP
- tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i32 7, i32 -3) nounwind
- ret void
-}
-
-define void @constraint_J() nounwind {
-; Now J with 0
-; ALL-LABEL: constraint_J:
-; ALL: #APP
-; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0
-; ALL: #NO_APP
- tail call i32 asm sideeffect "addiu $0, $1, $2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
- ret void
-}
-
-define void @constraint_K() nounwind {
-; Now K with 64
-; ALL: #APP
-; GAS: addu ${{[0-9]+}}, ${{[0-9]+}}, 64
-; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 64
-; ALL: #NO_APP
- tail call i16 asm sideeffect "addu $0, $1, $2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind
- ret void
-}
-
-define void @constraint_L() nounwind {
-; Now L with 0x00100000
-; ALL: #APP
-; ALL: add ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
-; ALL: #NO_APP
- tail call i32 asm sideeffect "add $0, $1, $3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind
- ret void
-}
-
-define void @constraint_N() nounwind {
-; Now N with -3
-; ALL: #APP
-; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
-; ALL: #NO_APP
- tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,N"(i32 7, i32 -3) nounwind
- ret void
-}
-
-define void @constraint_O() nounwind {
-; Now O with -3
-; ALL: #APP
-; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
-; ALL: #NO_APP
- tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,O"(i32 7, i16 -3) nounwind
- ret void
-}
-
-define void @constraint_P() nounwind {
-; Now P with 65535
-; ALL: #APP
-; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 65535
-; ALL: #NO_APP
- tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,P"(i32 7, i32 65535) nounwind
- ret void
-}
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_R.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_R.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_R.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_R.ll (removed)
@@ -1,60 +0,0 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
-
- at data = global [8193 x i32] zeroinitializer
-
-define void @R(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: R:
-
- call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
-
- ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK: #APP
- ; CHECK: lw $1, 0($[[BASEPTR]])
- ; CHECK: #NO_APP
-
- ret void
-}
-
-define void @R_offset_4(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: R_offset_4:
-
- call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
-
- ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK: #APP
- ; CHECK: lw $1, 4($[[BASEPTR]])
- ; CHECK: #NO_APP
-
- ret void
-}
-
-define void @R_offset_254(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: R_offset_254:
-
- call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 63))
-
- ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK: #APP
- ; CHECK: lw $1, 252($[[BASEPTR]])
- ; CHECK: #NO_APP
-
- ret void
-}
-
-define void @R_offset_256(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: R_offset_256:
-
- call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 64))
-
- ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
- ; CHECK: #APP
- ; CHECK: lw $1, 0($[[BASEPTR2]])
- ; CHECK: #NO_APP
-
- ret void
-}
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_ZC.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_ZC.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_ZC.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_ZC.ll (removed)
@@ -1,167 +0,0 @@
-; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,09BIT
-; RUN: llc -march=mipsel -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,12BIT
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,16BIT
-
- at data = global [8193 x i32] zeroinitializer
-
-define void @ZC(i32 *%p) nounwind {
-entry:
- ; ALL-LABEL: ZC:
-
- call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
-
- ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; ALL: #APP
- ; ALL: lw $1, 0($[[BASEPTR]])
- ; ALL: #NO_APP
-
- ret void
-}
-
-define void @ZC_offset_n4(i32 *%p) nounwind {
-entry:
- ; ALL-LABEL: ZC_offset_n4:
-
- call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 -1))
-
- ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; ALL: #APP
- ; ALL: lw $1, -4($[[BASEPTR]])
- ; ALL: #NO_APP
-
- ret void
-}
-
-define void @ZC_offset_4(i32 *%p) nounwind {
-entry:
- ; ALL-LABEL: ZC_offset_4:
-
- call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
-
- ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; ALL: #APP
- ; ALL: lw $1, 4($[[BASEPTR]])
- ; ALL: #NO_APP
-
- ret void
-}
-
-define void @ZC_offset_252(i32 *%p) nounwind {
-entry:
- ; ALL-LABEL: ZC_offset_252:
-
- call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 63))
-
- ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; ALL: #APP
- ; ALL: lw $1, 252($[[BASEPTR]])
- ; ALL: #NO_APP
-
- ret void
-}
-
-define void @ZC_offset_256(i32 *%p) nounwind {
-entry:
- ; ALL-LABEL: ZC_offset_256:
-
- call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 64))
-
- ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
-
- ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 256
-
- ; ALL: #APP
-
- ; 09BIT: lw $1, 0($[[BASEPTR2]])
- ; 12BIT: lw $1, 256($[[BASEPTR]])
- ; 16BIT: lw $1, 256($[[BASEPTR]])
-
- ; ALL: #NO_APP
-
- ret void
-}
-
-define void @ZC_offset_2044(i32 *%p) nounwind {
-entry:
- ; ALL-LABEL: ZC_offset_2044:
-
- call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 511))
-
- ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
-
- ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 2044
-
- ; ALL: #APP
-
- ; 09BIT: lw $1, 0($[[BASEPTR2]])
- ; 12BIT: lw $1, 2044($[[BASEPTR]])
- ; 16BIT: lw $1, 2044($[[BASEPTR]])
-
- ; ALL: #NO_APP
-
- ret void
-}
-
-define void @ZC_offset_2048(i32 *%p) nounwind {
-entry:
- ; ALL-LABEL: ZC_offset_2048:
-
- call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 512))
-
- ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
-
- ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 2048
- ; 12BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 2048
-
- ; ALL: #APP
-
- ; 09BIT: lw $1, 0($[[BASEPTR2]])
- ; 12BIT: lw $1, 0($[[BASEPTR2]])
- ; 16BIT: lw $1, 2048($[[BASEPTR]])
-
- ; ALL: #NO_APP
-
- ret void
-}
-
-define void @ZC_offset_32764(i32 *%p) nounwind {
-entry:
- ; ALL-LABEL: ZC_offset_32764:
-
- call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8191))
-
- ; ALL-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
-
- ; 09BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 32764
- ; 12BIT: addiu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], 32764
-
- ; ALL: #APP
-
- ; 09BIT: lw $1, 0($[[BASEPTR2]])
- ; 12BIT: lw $1, 0($[[BASEPTR2]])
- ; 16BIT: lw $1, 32764($[[BASEPTR]])
-
- ; ALL: #NO_APP
-
- ret void
-}
-
-define void @ZC_offset_32768(i32 *%p) nounwind {
-entry:
- ; ALL-LABEL: ZC_offset_32768:
-
- call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8192))
-
- ; ALL-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; ALL-DAG: ori $[[T0:[0-9]+]], $zero, 32768
-
- ; 09BIT: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
- ; 12BIT: addu16 $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
- ; 16BIT: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
-
- ; ALL: #APP
- ; ALL: lw $1, 0($[[BASEPTR2]])
- ; ALL: #NO_APP
-
- ret void
-}
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_m.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_m.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_m.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_m.ll (removed)
@@ -1,61 +0,0 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
-
- at data = global [8193 x i32] zeroinitializer
-
-define void @m(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: m:
-
- call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
-
- ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK: #APP
- ; CHECK: lw $1, 0($[[BASEPTR]])
- ; CHECK: #NO_APP
-
- ret void
-}
-
-define void @m_offset_4(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: m_offset_4:
-
- call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
-
- ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK: #APP
- ; CHECK: lw $1, 4($[[BASEPTR]])
- ; CHECK: #NO_APP
-
- ret void
-}
-
-define void @m_offset_32764(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: m_offset_32764:
-
- call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8191))
-
- ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK: #APP
- ; CHECK: lw $1, 32764($[[BASEPTR]])
- ; CHECK: #NO_APP
-
- ret void
-}
-
-define void @m_offset_32768(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: m_offset_32768:
-
- call void asm sideeffect "lw $$1, $0", "*m,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8192))
-
- ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK-DAG: ori $[[T0:[0-9]+]], $zero, 32768
- ; CHECK: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
- ; CHECK: #APP
- ; CHECK: lw $1, 0($[[BASEPTR2]])
- ; CHECK: #NO_APP
-
- ret void
-}
Removed: llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_o.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_o.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_o.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasm_constraint_o.ll (removed)
@@ -1,61 +0,0 @@
-; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s
-
- at data = global [8193 x i32] zeroinitializer
-
-define void @o(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: o:
-
- call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 0))
-
- ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK: #APP
- ; CHECK: lw $1, 0($[[BASEPTR]])
- ; CHECK: #NO_APP
-
- ret void
-}
-
-define void @o_offset_4(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: o_offset_4:
-
- call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 1))
-
- ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK: #APP
- ; CHECK: lw $1, 4($[[BASEPTR]])
- ; CHECK: #NO_APP
-
- ret void
-}
-
-define void @o_offset_32764(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: o_offset_32764:
-
- call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8191))
-
- ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK: #APP
- ; CHECK: lw $1, 32764($[[BASEPTR]])
- ; CHECK: #NO_APP
-
- ret void
-}
-
-define void @o_offset_32768(i32 *%p) nounwind {
-entry:
- ; CHECK-LABEL: o_offset_32768:
-
- call void asm sideeffect "lw $$1, $0", "*o,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193 x i32]* @data, i32 0, i32 8192))
-
- ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
- ; CHECK-DAG: ori $[[T0:[0-9]+]], $zero, 32768
- ; CHECK: addu $[[BASEPTR2:[0-9]+]], $[[BASEPTR]], $[[T0]]
- ; CHECK: #APP
- ; CHECK: lw $1, 0($[[BASEPTR2]])
- ; CHECK: #NO_APP
-
- ret void
-}
Removed: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll?rev=366301&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (removed)
@@ -1,67 +0,0 @@
-; RUN: llc -march=mips -relocation-model=pic < %s \
-; RUN: | FileCheck --check-prefixes=CHECK,EB %s
-; RUN: llc -march=mipsel -relocation-model=pic < %s \
-; RUN: | FileCheck --check-prefixes=CHECK,EL %s
-
-; Simple memory
- at g1 = external global i32
-
-define i32 @f1(i32 %x) nounwind {
-entry:
-; CHECK-LABEL: f1:
-; CHECK: #APP
-; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp)
-; CHECK: #NO_APP
-; CHECK: lw $[[T1:[0-9]+]], %got(g1)
-; CHECK: #APP
-; CHECK: lw $[[T3:[0-9]+]], [[OFFSET]]($sp)
-; CHECK: #NO_APP
-; CHECK: sw $[[T3]], 0($[[T1]])
-
- %l1 = alloca i32, align 4
- call void asm "sw $1, $0", "=*m,r"(i32* %l1, i32 %x) nounwind
- %0 = call i32 asm "lw $0, $1", "=r,*m"(i32* %l1) nounwind
- store i32 %0, i32* @g1, align 4
- ret i32 %0
-}
-
-; CHECK-LABEL: main:
-; "D": Second word of a double word. This works for any memory element
-; double or single.
-; CHECK: #APP
-; CHECK: lw ${{[0-9]+}}, 16(${{[0-9]+}})
-; CHECK: #NO_APP
-
-; No "D": First word of a double word. This works for any memory element
-; double or single.
-; CHECK: #APP
-; CHECK: lw ${{[0-9]+}}, 12(${{[0-9]+}})
-; CHECK: #NO_APP
-
-; "M": High-order word of a double word.
-; CHECK: #APP
-; EB: lw ${{[0-9]+}}, 12(${{[0-9]+}})
-; EL: lw ${{[0-9]+}}, 16(${{[0-9]+}})
-; CHECK: #NO_APP
-
-; "L": Low-order word of a double word.
-; CHECK: #APP
-; EB: lw ${{[0-9]+}}, 16(${{[0-9]+}})
-; EL: lw ${{[0-9]+}}, 12(${{[0-9]+}})
-; CHECK: #NO_APP
-
- at b = common global [20 x i32] zeroinitializer, align 4
-
-define void @main() {
-entry:
-; Second word:
- tail call void asm sideeffect " lw $0, ${1:D}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
-; First word. Notice, no 'D':
- tail call void asm sideeffect " lw $0, ${1}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
-
-; High-order part.
- tail call void asm sideeffect " lw $0, ${1:M}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
-; Low-order part.
- tail call void asm sideeffect " lw $0, ${1:L}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3))
- ret void
-}
More information about the llvm-commits
mailing list