[llvm] r366301 - [mips] Use mult/mflo pattern on 64-bit targets prior to MIPS64

Simon Atanasyan via llvm-commits llvm-commits at lists.llvm.org
Wed Jul 17 01:11:40 PDT 2019


Author: atanasyan
Date: Wed Jul 17 01:11:40 2019
New Revision: 366301

URL: http://llvm.org/viewvc/llvm-project?rev=366301&view=rev
Log:
[mips] Use mult/mflo pattern on 64-bit targets prior to MIPS64

The `MUL` instruction is available starting from the MIPS32/MIPS64 targets.

Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=366301&r1=366300&r2=366301&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Jul 17 01:11:40 2019
@@ -853,7 +853,7 @@ def : MipsPat<(i64 (sext (i32 (sub GPR32
               (SUBu GPR32:$src, GPR32:$src2), sub_32)>;
 def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))),
               (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
-              (MUL GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS3_NOT_32R6_64R6;
+              (MUL GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS32_NOT_32R6_64R6;
 def : MipsPat<(i64 (sext (i32 (MipsMFHI ACC64:$src)))),
               (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
               (PseudoMFHI ACC64:$src), sub_32)>;

Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll?rev=366301&r1=366300&r2=366301&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll Wed Jul 17 01:11:40 2019
@@ -155,6 +155,9 @@ entry:
   ; M2:         mult    $4, $5
   ; M2:         mflo    $2
 
+  ; M4:         mult    $4, $5
+  ; M4:         mflo    $1
+
   ; 32R1-R5:    mul     $2, $4, $5
   ; 32R6:       mul     $2, $4, $5
 




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