[llvm] r366005 - [ARM] MVE integer abs

[David Green via llvm-commits]

Author: dmgreen
Date: Sat Jul 13 07:58:32 2019
New Revision: 366005

URL: http://llvm.org/viewvc/llvm-project?rev=366005&view=rev
Log:
[ARM] MVE integer abs

Similar to floating point abs, we also have instructions for integers.

Differential Revision: https://reviews.llvm.org/D64027

Added:
    llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrMVE.td

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=366005&r1=366004&r2=366005&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sat Jul 13 07:58:32 2019
@@ -254,6 +254,7 @@ void ARMTargetLowering::addMVEVectorType
     setOperationAction(ISD::SMAX, VT, Legal);
     setOperationAction(ISD::UMIN, VT, Legal);
     setOperationAction(ISD::UMAX, VT, Legal);
+    setOperationAction(ISD::ABS, VT, Legal);
 
     // No native support for these.
     setOperationAction(ISD::UDIV, VT, Expand);

Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=366005&r1=366004&r2=366005&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Sat Jul 13 07:58:32 2019
@@ -2189,6 +2189,15 @@ def MVE_VABSs8  : MVE_VABSNEG_int<"vabs"
 def MVE_VABSs16 : MVE_VABSNEG_int<"vabs", "s16", 0b01, 0b0>;
 def MVE_VABSs32 : MVE_VABSNEG_int<"vabs", "s32", 0b10, 0b0>;
 
+let Predicates = [HasMVEInt] in {
+  def : Pat<(v16i8 (abs (v16i8 MQPR:$v))),
+            (v16i8 (MVE_VABSs8 $v))>;
+  def : Pat<(v8i16 (abs (v8i16 MQPR:$v))),
+            (v8i16 (MVE_VABSs16 $v))>;
+  def : Pat<(v4i32 (abs (v4i32 MQPR:$v))),
+            (v4i32 (MVE_VABSs32 $v))>;
+}
+
 def MVE_VNEGs8  : MVE_VABSNEG_int<"vneg", "s8",  0b00, 0b1>;
 def MVE_VNEGs16 : MVE_VABSNEG_int<"vneg", "s16", 0b01, 0b1>;
 def MVE_VNEGs32 : MVE_VABSNEG_int<"vneg", "s32", 0b10, 0b1>;

Added: llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll?rev=366005&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll Sat Jul 13 07:58:32 2019
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
+
+define arm_aapcs_vfpcc <16 x i8> @abs_v16i8(<16 x i8> %s1) {
+; CHECK-LABEL: abs_v16i8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vabs.s8 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp slt <16 x i8> %s1, zeroinitializer
+  %1 = sub nsw <16 x i8> zeroinitializer, %s1
+  %2 = select <16 x i1> %0, <16 x i8> %1, <16 x i8> %s1
+  ret <16 x i8> %2
+}
+
+define arm_aapcs_vfpcc <8 x i16> @abs_v8i16(<8 x i16> %s1) {
+; CHECK-LABEL: abs_v8i16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vabs.s16 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp slt <8 x i16> %s1, zeroinitializer
+  %1 = sub nsw <8 x i16> zeroinitializer, %s1
+  %2 = select <8 x i1> %0, <8 x i16> %1, <8 x i16> %s1
+  ret <8 x i16> %2
+}
+
+define arm_aapcs_vfpcc <4 x i32> @abs_v4i32(<4 x i32> %s1) {
+; CHECK-LABEL: abs_v4i32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vabs.s32 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = icmp slt <4 x i32> %s1, zeroinitializer
+  %1 = sub nsw <4 x i32> zeroinitializer, %s1
+  %2 = select <4 x i1> %0, <4 x i32> %1, <4 x i32> %s1
+  ret <4 x i32> %2
+}