[llvm] r366004 - [ARM] MVE integer min and max
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 13 07:48:55 PDT 2019
Author: dmgreen
Date: Sat Jul 13 07:48:54 2019
New Revision: 366004
URL: http://llvm.org/viewvc/llvm-project?rev=366004&view=rev
Log:
[ARM] MVE integer min and max
This simply makes the MVE integer min and max instructions legal and adds the
relevant patterns for them.
Differential Revision: https://reviews.llvm.org/D64026
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=366004&r1=366003&r2=366004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sat Jul 13 07:48:54 2019
@@ -250,6 +250,10 @@ void ARMTargetLowering::addMVEVectorType
setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
+ setOperationAction(ISD::SMIN, VT, Legal);
+ setOperationAction(ISD::SMAX, VT, Legal);
+ setOperationAction(ISD::UMIN, VT, Legal);
+ setOperationAction(ISD::UMAX, VT, Legal);
// No native support for these.
setOperationAction(ISD::UDIV, VT, Expand);
Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=366004&r1=366003&r2=366004&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Sat Jul 13 07:48:54 2019
@@ -907,6 +907,36 @@ multiclass MVE_VMINMAX_all_sizes<string
defm MVE_VMAX : MVE_VMINMAX_all_sizes<"vmax", 0b0>;
defm MVE_VMIN : MVE_VMINMAX_all_sizes<"vmin", 0b1>;
+let Predicates = [HasMVEInt] in {
+ def : Pat<(v16i8 (smin (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
+ (v16i8 (MVE_VMINs8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
+ def : Pat<(v8i16 (smin (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
+ (v8i16 (MVE_VMINs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
+ def : Pat<(v4i32 (smin (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
+ (v4i32 (MVE_VMINs32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
+
+ def : Pat<(v16i8 (smax (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
+ (v16i8 (MVE_VMAXs8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
+ def : Pat<(v8i16 (smax (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
+ (v8i16 (MVE_VMAXs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
+ def : Pat<(v4i32 (smax (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
+ (v4i32 (MVE_VMAXs32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
+
+ def : Pat<(v16i8 (umin (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
+ (v16i8 (MVE_VMINu8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
+ def : Pat<(v8i16 (umin (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
+ (v8i16 (MVE_VMINu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
+ def : Pat<(v4i32 (umin (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
+ (v4i32 (MVE_VMINu32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
+
+ def : Pat<(v16i8 (umax (v16i8 MQPR:$val1), (v16i8 MQPR:$val2))),
+ (v16i8 (MVE_VMAXu8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>;
+ def : Pat<(v8i16 (umax (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))),
+ (v8i16 (MVE_VMAXu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>;
+ def : Pat<(v4i32 (umax (v4i32 MQPR:$val1), (v4i32 MQPR:$val2))),
+ (v4i32 (MVE_VMAXu32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2)))>;
+}
+
// end of mve_comp instructions
// start of mve_imm_shift instructions
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll?rev=366004&r1=366003&r2=366004&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll Sat Jul 13 07:48:54 2019
@@ -2,6 +2,140 @@
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
+define arm_aapcs_vfpcc <16 x i8> @smin_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
+; CHECK-LABEL: smin_v16i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmin.s8 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp slt <16 x i8> %s1, %s2
+ %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
+ ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @smin_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
+; CHECK-LABEL: smin_v8i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmin.s16 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp slt <8 x i16> %s1, %s2
+ %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
+ ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @smin_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
+; CHECK-LABEL: smin_v4i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmin.s32 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp slt <4 x i32> %s1, %s2
+ %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <16 x i8> @umin_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
+; CHECK-LABEL: umin_v16i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmin.u8 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp ult <16 x i8> %s1, %s2
+ %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
+ ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @umin_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
+; CHECK-LABEL: umin_v8i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmin.u16 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp ult <8 x i16> %s1, %s2
+ %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
+ ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @umin_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
+; CHECK-LABEL: umin_v4i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmin.u32 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp ult <4 x i32> %s1, %s2
+ %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
+ ret <4 x i32> %1
+}
+
+
+define arm_aapcs_vfpcc <16 x i8> @smax_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
+; CHECK-LABEL: smax_v16i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmax.s8 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp sgt <16 x i8> %s1, %s2
+ %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
+ ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @smax_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
+; CHECK-LABEL: smax_v8i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmax.s16 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp sgt <8 x i16> %s1, %s2
+ %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
+ ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @smax_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
+; CHECK-LABEL: smax_v4i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmax.s32 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp sgt <4 x i32> %s1, %s2
+ %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
+ ret <4 x i32> %1
+}
+
+define arm_aapcs_vfpcc <16 x i8> @umax_v16i8(<16 x i8> %s1, <16 x i8> %s2) {
+; CHECK-LABEL: umax_v16i8:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmax.u8 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp ugt <16 x i8> %s1, %s2
+ %1 = select <16 x i1> %0, <16 x i8> %s1, <16 x i8> %s2
+ ret <16 x i8> %1
+}
+
+define arm_aapcs_vfpcc <8 x i16> @umax_v8i16(<8 x i16> %s1, <8 x i16> %s2) {
+; CHECK-LABEL: umax_v8i16:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmax.u16 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp ugt <8 x i16> %s1, %s2
+ %1 = select <8 x i1> %0, <8 x i16> %s1, <8 x i16> %s2
+ ret <8 x i16> %1
+}
+
+define arm_aapcs_vfpcc <4 x i32> @umax_v4i32(<4 x i32> %s1, <4 x i32> %s2) {
+; CHECK-LABEL: umax_v4i32:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vmax.u32 q0, q0, q1
+; CHECK-NEXT: bx lr
+entry:
+ %0 = icmp ugt <4 x i32> %s1, %s2
+ %1 = select <4 x i1> %0, <4 x i32> %s1, <4 x i32> %s2
+ ret <4 x i32> %1
+}
+
+
define arm_aapcs_vfpcc <4 x float> @maxnm_float32_t(<4 x float> %src1, <4 x float> %src2) {
; CHECK-MVE-LABEL: maxnm_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry
More information about the llvm-commits
mailing list