[PATCH] D64446: [AMDGPU] gfx908 mAI instructions, MC part

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec marked 3 inline comments as done.
rampitec added inline comments.


================
Comment at: include/llvm/IR/IntrinsicsAMDGPU.td:1648
+  [llvm_float_ty, llvm_float_ty, llvm_v32i32_ty,
+   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;
+
----------------
arsenm wrote:
> Should these be speculatable?
I do not think so. They are crosslane.


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Comment at: lib/Target/AMDGPU/AMDGPURegAsmNames.inc.cpp:353
 
+static const char *const AGPR32RegNames[] = {
+    "a0",   "a1",   "a2",   "a3",   "a4",   "a5",   "a6",   "a7",   "a8",
----------------
arsenm wrote:
> We should probably get around to making tablegen produce these tables
Likely. This file is growing.


================
Comment at: lib/Target/AMDGPU/SIInstrFormats.td:125
+  // This bit indicates that this is one of MFMA instructions.
+  field bit IsMAI = 0;
+
----------------
arsenm wrote:
> It's not obvious to me what MAI stands for
That is how these are called in the spec. I assume when we upload the spec it will make more sense. But generally Matrix Arithmetic ISA.


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  https://reviews.llvm.org/D64446/new/

https://reviews.llvm.org/D64446