[PATCH] D64237: [test-suite] Fix RISC-V Support in benchmark 1.3.0

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
lenary added a reviewer: lebedev.ri.
Herald added subscribers: llvm-commits, rkruppe, rogfer01, shiva0217, kito-cheng.
Herald added a project: LLVM.

Fixed by backporting the upstream fix from here:

  https://github.com/google/benchmark/pull/833


Repository:
  rT test-suite

https://reviews.llvm.org/D64237

Files:
  MicroBenchmarks/libs/benchmark-1.3.0/src/cycleclock.h


Index: MicroBenchmarks/libs/benchmark-1.3.0/src/cycleclock.h
===================================================================
--- MicroBenchmarks/libs/benchmark-1.3.0/src/cycleclock.h
+++ MicroBenchmarks/libs/benchmark-1.3.0/src/cycleclock.h
@@ -164,6 +164,21 @@
   uint64_t tsc;
   asm("stck %0" : "=Q" (tsc) : : "cc");
   return tsc;
+#elif defined(__riscv) // RISC-V
+  // Use RDCYCLE (and RDCYCLEH on riscv32)
+#if __riscv_xlen == 32
+  uint64_t cycles_low, cycles_hi0, cycles_hi1;
+  asm("rdcycleh %0" : "=r"(cycles_hi0));
+  asm("rdcycle %0" : "=r"(cycles_lo));
+  asm("rdcycleh %0" : "=r"(cycles_hi1));
+  // This matches the PowerPC overflow detection, above
+  cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
+  return (cycles_hi1 << 32) | cycles_lo;
+#else
+  uint64_t cycles;
+  asm("rdcycle %0" : "=r"(cycles));
+  return cycles;
+#endif
 #else
 // The soft failover to a generic implementation is automatic only for ARM.
 // For other platforms the developer is expected to make an attempt to create


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