[PATCH] D63924: [AMDGPU] Created a sub-register class for the return address operand in the return instruction.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:2237
+        &AMDGPU::CCR_SGPR_64RegClass), MVT::i64);
+    Chain = DAG.getCopyToReg(Chain, DL, ReturnAddrVirtualReg, ReturnAddrReg, Flag);
     Flag = Chain.getValue(1);
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This line looks too long? Run clang-format?


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:492
+// CCR (call clobbered registers) SGPR 64-bit registers
+def CCR_SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32, (add (trunc SGPR_64, 16))> {
+  let CopyCost = 1;
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You should bee able to use SGPR_64.RegTypes to avoid repeating the type list


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:493-494
+def CCR_SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32, (add (trunc SGPR_64, 16))> {
+  let CopyCost = 1;
+  let AllocationPriority = 9;
+}
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You can also avoid repeating these with SGPR_64.CopyCost, and AllocationPriority


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63924/new/

https://reviews.llvm.org/D63924