[PATCH] D63924: [AMDGPU] Created a sub-register class for the return address operand in the return instruction.

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas updated this revision to Diff 207250.
cdevadas added a comment.

Parameterized the existing operand class 'SOP1_1' to accommodate different register classes.
Added explicit check for the register pair in return instruction, 's_setpc_b64' (for nested-calls.ll test)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63924/new/

https://reviews.llvm.org/D63924

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIRegisterInfo.td
  lib/Target/AMDGPU/SOPInstructions.td
  test/CodeGen/AMDGPU/call-graph-register-usage.ll
  test/CodeGen/AMDGPU/call-preserved-registers.ll
  test/CodeGen/AMDGPU/callee-frame-setup.ll
  test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
  test/CodeGen/AMDGPU/chain-hi-to-lo.ll
  test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  test/CodeGen/AMDGPU/llvm.log.f16.ll
  test/CodeGen/AMDGPU/llvm.log10.f16.ll
  test/CodeGen/AMDGPU/load-lo16.ll
  test/CodeGen/AMDGPU/nested-calls.ll
  test/CodeGen/AMDGPU/wave32.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D63924.207250.patch
Type: text/x-patch
Size: 20481 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190701/c7b1c2c6/attachment.bin>