[PATCH] D64125: [RISCV] Support @llvm.readcyclecounter() Intrinsic

[Sam Elliott via Phabricator via llvm-commits]

lenary marked 13 inline comments as done.
lenary added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1062
+let Predicates = [IsRV64] in
+def : Pat<(readcyclecounter), (CSRRS 0xC00, X0)>;
+// On RV32, ReadCycleWide is inserted and expanded to the suggested rdcycle[h] loop.
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simoncook wrote:
> This should have a comment, like on line 611 which notes 0xc00 is a CSR address rather than a random constant.
> 
> (I also think it would be nice to have patterns select named InstAliases to use the `rdcycle` instruction alias directly, but it seems TableGen doesn't support doing such a thing)
I'm going to wait for D64139 to land, and then use the constants introduced there.


Repository:
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  https://reviews.llvm.org/D64125/new/

https://reviews.llvm.org/D64125