[llvm] r365023 - [mips] Add SIGRIE, GINVI, GINVT to general scheduling definitions

[Simon Atanasyan via llvm-commits]

Author: atanasyan
Date: Wed Jul  3 03:33:16 2019
New Revision: 365023

URL: http://llvm.org/viewvc/llvm-project?rev=365023&view=rev
Log:
[mips] Add SIGRIE,GINVI,GINVT to general scheduling definitions

Modified:
    llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td

Modified: llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td?rev=365023&r1=365022&r2=365023&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsScheduleGeneric.td Wed Jul  3 03:33:16 2019
@@ -311,7 +311,7 @@ def : InstRW<[GenericWriteJumpAndLink],
 def : InstRW<[GenericWriteJump], (instrs BC, BC2EQZ, BC2NEZ, BEQC, BEQZC, BGEC,
                                   BGEUC, BGEZC, BGTZC, BLEZC, BLTC, BLTUC,
                                   BLTZC, BNEC, BNEZC, BNVC, BOVC, JIC, JR_HB_R6,
-                                  PseudoIndirectBranchR6,
+                                  SIGRIE, PseudoIndirectBranchR6,
                                   PseudoIndrectHazardBranchR6)>;
 
 def : InstRW<[GenericWriteJump], (instrs TAILCALLR6REG, TAILCALLHBR6REG)>;
@@ -377,7 +377,7 @@ def : InstRW<[GenericWriteJump], (instrs
                                   BNEZC16_MMR6, BNEZC_MMR6, BNVC_MMR6,
                                   BOVC_MMR6, DERET_MMR6, ERETNC_MMR6,
                                   ERET_MMR6, JIC_MMR6, JRADDIUSP, JRC16_MM,
-                                  JRC16_MMR6, JRCADDIUSP_MMR6,
+                                  JRC16_MMR6, JRCADDIUSP_MMR6, SIGRIE_MMR6,
                                   PseudoIndirectBranch_MMR6)>;
 
 def : InstRW<[GenericWriteJumpAndLink], (instrs BALC_MMR6, BEQZALC_MMR6,
@@ -589,6 +589,8 @@ def : InstRW<[GenericWritePref], (instrs
 
 def : InstRW<[GenericWriteCache], (instrs CACHE_R6)>;
 
+def : InstRW<[GenericWriteSync], (instrs GINVI, GINVT)>;
+
 // MIPS32 EVA
 // ==========
 
@@ -649,6 +651,7 @@ def : InstRW<[GenericWritePref], (instrs
 def : InstRW<[GenericWriteCache], (instrs CACHE_MM)>;
 
 def : InstRW<[GenericWriteSync], (instrs SYNC_MM, SYNCI_MM)>;
+def : InstRW<[GenericWriteSync], (instrs GINVI_MMR6, GINVT_MMR6)>;
 
 // microMIPS32r6
 // =============