[PATCH] D30324: [ARM] Thumb2: favor R4-R7 over R12/LR in allocation order when opt for minsize

[James Molloy via Phabricator via llvm-commits]

jmolloy added inline comments.


================
Comment at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:295
+
+  virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF) const {
+    return false;
----------------
All virtual functions should have a docstring.


================
Comment at: llvm/lib/CodeGen/RegisterClassInfo.cpp:118
 
-    if (CalleeSavedAliases[PhysReg])
+    if (CalleeSavedAliases[PhysReg] && !STI.ignoreCSRForAllocationOrder(*MF))
       // PhysReg aliases a CSR, save it for later.
----------------
Although you're not using it here, it seems to me very natural for such a callback to take the PhysReg too.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D30324/new/

https://reviews.llvm.org/D30324