[PATCH] D63924: [AMDGPU] Created a sub-register class for the return address operand in the return instruction.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SOPInstructions.td:133-137
+// 64-bit input (subset of SGPR_64) , no output
+class SOP1_64_2 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
+  opName, (outs), (ins CCR_SGPR_64:$src0), "$src0", pattern> {
+  let has_sdst = 0;
+}
----------------
The name doesn't match what this is for. I would rather not introduce a separate instruction class for this. You can instead parameterize the existing class with the (ins) for the instruction, defaulting to (ins SReg_64:$src0)


================
Comment at: test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll:32
 ; GCN-NEXT:    s_add_u32 s32, s32, 0x400
-; GCN-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN-NEXT:    s_or_saveexec_b64 [[COPY_EXEC0:s\[[0-9]+:[0-9]+\]]], -1{{$}}
 ; GCN-NEXT:    buffer_store_dword v32, off, s[0:3], s5 ; 4-byte Folded Spill
----------------
It looks like you manually added these checks instead of using update_llc_test_checks?


================
Comment at: test/CodeGen/AMDGPU/nested-calls.ll:33
 ; GCN: s_sub_u32 s32, s32, 0x400
 ; GCN: s_setpc_b64
 define void @test_func_call_external_void_func_i32_imm() #0 {
----------------
Are the results actually better looking? Can you add explicit checks for the register s_setpc_b64 is using?


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63924/new/

https://reviews.llvm.org/D63924