[PATCH] D63816: [ARM] WLS/LE Code Generation

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer accepted this revision.
SjoerdMeijer added a comment.
This revision is now accepted and ready to land.

This looks fine as an initial commit to me. I.e., this can be followed up, addressing the TODOs, to produce even more efficient code and handle more cases.



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Comment at: lib/Target/ARM/ARMInstrInfo.td:103
+// TODO Add another operand for 'Size' so that we can re-use this node when we
+// start supporting *TP versions.
+def SDT_ARMWhileLoop : SDTypeProfile<0, 2, [SDTCisVT<0, i32>,
----------------
nit:

  // start supporting *TP versions

I think for clarity I would spell this out as the tail-predicated versions


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Comment at: test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll:4
+
+; Not implemented as a mir test so that changes the generic HardwareLoop can
+; also be tested. These functions have been taken from
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nit:

 ".. that changes the generic HardwareLoop .."

->

".. that changes in the generic HardwareLoop.. "?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63816/new/

https://reviews.llvm.org/D63816