[PATCH] D63924: [AMDGPU] Created a sub-register class for the return address operand in the return instruction.

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas created this revision.
cdevadas added a reviewer: arsenm.
Herald added subscribers: llvm-commits, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

Function return instruction lowering, currently uses the fixed register pair, s[30:31] for holding the return address.
It can be any SGPR pair other than the CSRs. Created an SGPR pair sub-register class exclusive of the CSRs, and used this register class while lowering the return instruction.


Repository:
  rL LLVM

https://reviews.llvm.org/D63924

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIRegisterInfo.td
  lib/Target/AMDGPU/SOPInstructions.td
  test/CodeGen/AMDGPU/call-graph-register-usage.ll
  test/CodeGen/AMDGPU/call-preserved-registers.ll
  test/CodeGen/AMDGPU/callee-frame-setup.ll
  test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
  test/CodeGen/AMDGPU/chain-hi-to-lo.ll
  test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  test/CodeGen/AMDGPU/llvm.log.f16.ll
  test/CodeGen/AMDGPU/llvm.log10.f16.ll
  test/CodeGen/AMDGPU/load-lo16.ll
  test/CodeGen/AMDGPU/nested-calls.ll
  test/CodeGen/AMDGPU/wave32.ll

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