[PATCH] D62100: [DAGCombine][X86][AMDGPU][AArch64] (srl (shl x, c1), c2) with c1 != c2 handling

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: test/CodeGen/X86/rotate-extract-vector.ll:168
+; X64:       # %bb.0:
+; X64-NEXT:    vpbroadcastq {{.*#+}} ymm1 = [16383,16383,16383,16383]
+; X64-NEXT:    vpsrlq $39, %ymm0, %ymm2
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xbolva00 wrote:
> @rksimon is  this better?
Unlikely - a pair of shifts by uniform constants is almost certainly better


Repository:
  rL LLVM

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  https://reviews.llvm.org/D62100/new/

https://reviews.llvm.org/D62100