[PATCH] D62100: [DAGCombine][X86][AMDGPU][AArch64] (srl (shl x, c1), c2) with c1 != c2 handling

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri marked 2 inline comments as done.
lebedev.ri added inline comments.


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Comment at: test/CodeGen/AArch64/arm64-bitfield-extract.ll:396
 ; LLC-NEXT:    ldr w8, [x0]
+; LLC-NEXT:    and w8, w8, #0x3ffffff8
 ; LLC-NEXT:    bfxil w8, w1, #16, #3
----------------
RKSimon wrote:
> lebedev.ri wrote:
> > After actually looking at `-debug` output, this regression happens because of `SimplifyDemandedBits()`,
> > which ignores `AArch64TargetLowering::isDesirableToCommuteWithShift()` override.
> > So when we get to `AArch64TargetLowering::isBitfieldExtractOp()`, we have
> > ```
> > t18: i32 = srl t15, Constant:i64<2>
> >   t15: i32 = or t26, t24
> >     t26: i32 = and t7, Constant:i32<1073741816>
> >       t7: i32,ch = load<(load 4 from %ir.y, align 8)> t0, t2, undef:i64
> >         t2: i64,ch = CopyFromReg t0, Register:i64 %0
> >           t1: i64 = Register %0
> >         t6: i64 = undef
> >       t25: i32 = Constant<1073741816>
> >     t24: i32 = and t12, Constant:i32<4>
> >       t12: i32 = srl t4, Constant:i64<16>
> >         t4: i32,ch = CopyFromReg t0, Register:i32 %1
> >           t3: i32 = Register %1
> >         t11: i64 = Constant<16>
> >       t23: i32 = Constant<4>
> >   t17: i64 = Constant<2>
> > ```
> > I'm not sure how to turn this pattern on it's head to produce `ubfx` again.
> @lebedev.ri Which SimplifyDemandedBits transforms is missing this?
The other way around, some SimplifyDemandedBits produces this, and the rest is unable to recover.


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  https://reviews.llvm.org/D62100/new/

https://reviews.llvm.org/D62100