[llvm] r364326 - [DAGCombine] combineRepeatedFPDivisors - recognize -1.0 / X as a reciprocal

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Jun 25 09:00:16 2019
New Revision: 364326

URL: http://llvm.org/viewvc/llvm-project?rev=364326&view=rev
Log:
[DAGCombine] combineRepeatedFPDivisors - recognize -1.0 / X as a reciprocal

Fixes issue identified by @nemanjai (Nemanja Ivanovic) in D62963 / rL363040 - infinite loop due to GetNegatedExpression fighting combineRepeatedFPDivisors resulting in fneg(fdiv(x,splat)) -> fneg(fmul(x,1.0/splat)) -> fmul(x,-1.0/splat) -> fmul(x,(-1.0 * 1.0)/splat) ......

Added:
    llvm/trunk/test/CodeGen/PowerPC/combine-fneg.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=364326&r1=364325&r2=364326&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jun 25 09:00:16 2019
@@ -12362,10 +12362,10 @@ SDValue DAGCombiner::combineRepeatedFPDi
   if (!UnsafeMath && !Flags.hasAllowReciprocal())
     return SDValue();
 
-  // Skip if current node is a reciprocal.
+  // Skip if current node is a reciprocal/fneg-reciprocal.
   SDValue N0 = N->getOperand(0);
   ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, /* AllowUndefs */ true);
-  if (N0CFP && N0CFP->isExactlyValue(1.0))
+  if (N0CFP && (N0CFP->isExactlyValue(1.0) || N0CFP->isExactlyValue(-1.0)))
     return SDValue();
 
   // Exit early if the target does not want this transform or if there can't

Added: llvm/trunk/test/CodeGen/PowerPC/combine-fneg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/combine-fneg.ll?rev=364326&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/combine-fneg.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/combine-fneg.ll Tue Jun 25 09:00:16 2019
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
+
+; Infinite loop identified in D62963.
+define <4 x double> @fneg_fdiv_splat(double %a0, <4 x double> %a1) {
+; CHECK-LABEL: fneg_fdiv_splat:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $f1 killed $f1 def $vsl1
+; CHECK-NEXT:    xxspltd 0, 1, 0
+; CHECK-NEXT:    addis 3, 2, .LCPI0_0 at toc@ha
+; CHECK-NEXT:    addi 3, 3, .LCPI0_0 at toc@l
+; CHECK-NEXT:    lxvd2x 1, 0, 3
+; CHECK-NEXT:    addis 3, 2, .LCPI0_1 at toc@ha
+; CHECK-NEXT:    xvredp 2, 0
+; CHECK-NEXT:    addi 3, 3, .LCPI0_1 at toc@l
+; CHECK-NEXT:    xxswapd 1, 1
+; CHECK-NEXT:    xvnmsubadp 1, 2, 0
+; CHECK-NEXT:    xvmaddadp 2, 2, 1
+; CHECK-NEXT:    lxvd2x 1, 0, 3
+; CHECK-NEXT:    xxswapd 1, 1
+; CHECK-NEXT:    xvmaddadp 1, 0, 2
+; CHECK-NEXT:    xvmsubadp 2, 2, 1
+; CHECK-NEXT:    xvmuldp 34, 34, 2
+; CHECK-NEXT:    xvmuldp 35, 35, 2
+; CHECK-NEXT:    blr
+entry:
+  %splat.splatinsert = insertelement <4 x double> undef, double %a0, i32 0
+  %splat.splat = shufflevector <4 x double> %splat.splatinsert, <4 x double> undef, <4 x i32> zeroinitializer
+  %div = fdiv fast <4 x double> %a1, %splat.splat
+  %sub = fsub fast <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>, %div
+  ret <4 x double> %sub
+}