[PATCH] D62890: [DAGCombiner] Merge consecutive stores of vector elements before types are legalized

[Ulrich Weigand via Phabricator via llvm-commits]

uweigand added a comment.

In D62890#1554934 <https://reviews.llvm.org/D62890#1554934>, @lkail wrote:

> Hi @jonpa, could you have a look if it is a real reg in SystemZ's change?


At a first glance this seems to be generating worse code now since we need to do all those permute-type instructions in order to get the bytes into the correct order in a single register to store ...   I'll clarify with the hardware folks which of the sequences would actually be preferable.

If it turns out that there are instances where *not* merging stores (even when it would be *possible*) is not preferred from a performance perspective, should common code use some cost function here?


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  rL LLVM

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  https://reviews.llvm.org/D62890/new/

https://reviews.llvm.org/D62890