[PATCH] D63494: [AMDGPU] Fix for branch offset hardware workaround

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: lib/Target/AMDGPU/SOPInstructions.td:943-945
+  let Inst{47-32} = 0x0000;
+  let Inst{54-48} = 0x00;
+  let Inst{63-55} = 0x17f; //encoding
----------------
arsenm wrote:
> I don't understand how this gets you a nop?
I guess s_nop opcode is 0, simm is 0 and SOPP encoding is 0x17f.
Maybe it would be more readable to write something like:

```
let Inst{63-55} = S_NOP.Inst{31-23}; // encoding
let Inst{54-48} = S_NOP.Inst{22-16}; // opcode

```


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63494/new/

https://reviews.llvm.org/D63494