[PATCH] D63494: [AMDGPU] Fix for branch offset hardware workaround

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/SOPInstructions.td:943-945
+  let Inst{47-32} = 0x0000;
+  let Inst{54-48} = 0x00;
+  let Inst{63-55} = 0x17f; //encoding
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I don't understand how this gets you a nop?


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Comment at: lib/Target/AMDGPU/SOPInstructions.td:948
+
+class SOPP64 <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
+  InstSI <(outs), ins, asm, pattern >, SOPPe64 <op>, Base_SOPP <asm> {
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SOPP_w_nop or something? The current naming sounds like an actually different encoding (same with SOPPe64)


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63494/new/

https://reviews.llvm.org/D63494